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general description the max6872/max6873 eeprom-configurable, multi- voltage supply sequencers/supervisors monitor several voltage detector inputs and four general-purpose logic inputs. the max6872/max6873 feature programmable outputs for highly configurable power-supply sequencing applications. the max6872 features six voltage detector inputs and eight programmable outputs, while the max6873 features four voltage detector inputs and five programmable outputs. manual reset and margin disable inputs offer additional flexibility. all voltage detectors offer two configurable thresholds for undervoltage/overvoltage or dual undervoltage detection. one high voltage input (in1) provides detec- tor threshold voltages from +2.5v to +13.2v in 50mv increments, or from +1.25v to +7.625v in 25mv incre- ments. a bipolar input (in2) provides detector threshold voltages from ?.5v to ?5.25v in 50mv increments, or from ?.25v to ?.625v in 25mv increments. positive inputs (in3?n6) provide detector threshold voltages from +1v to +5.5v in 20mv increments, or from +0.5v to +3.05v in 10mv increments. programmable output stages control power-supply sequencing or system resets/interrupts. programmable output options include: active-high, active-low, open- drain, weak pullup, push-pull, and charge pump. programmable timing delay blocks configure each output to wait between 25? and 1600ms before deasserting. a fault register logs the condition that caused each output to assert (undervoltage, overvoltage, manual reset, etc.). an smbus tm -/i 2 c-compatible, serial data interface programs and communicates with the configuration eeprom, the configuration registers, the internal 4kb user eeprom, and the fault registers of the max6872/max6873. the max6872/max6873 are available in a 7mm x 7mm x 0.8mm 32-pin thin qfn package and operate over the extended -40? to +85? temperature range. applications telecommunications/central office systems networking systems servers/workstations base stations storage equipment multimicroprocessor/voltage systems features ? six (max6872) or four (max6873) configurable input voltage detectors one high voltage input (+1.25v to +7.625v or +2.5v to +13.2v thresholds) one bipolar voltage input (1.25v to 7.625v or 2.5v to 15.25v thresholds) four (max6872) or two (max6873) positive voltage inputs (+0.5v to +3.05v or +1v to +5.5v thresholds) ? four general-purpose logic inputs ? two configurable watchdog timers ? eight (max6872) or five (max6873) programmable outputs active-high, active-low, open-drain, weak pullup, push-pull, charge-pump timing delays from 25s to 1600ms ? margining disable and manual reset controls ? 4kb internal user eeprom endurance: 100,000 erase/write cycles data retention: 10 years ? i 2 c/smbus-compatible serial configuration/communication interface ? 1% threshold accuracy max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors ________________________________________________________________ maxim integrated products 1 ordering information 19-3439; rev 0; 10/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available pin configurations, typical operating circuit, and selector guide appear at end of data sheet. part temp range pin- package pkg code max6872 etj -40? to +85? 32 thin qfn t3277-2 max6873 etj -40? to +85? 32 thin qfn t3277-2 smbus is a trademark of intel corp.
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in1 = +6.5v to +13.2v, v in2 = +10v, v in3 ? in6 = +2.7v to +5.5v, gpi_ = gnd, margin = mr = dbp, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (notes 1, 2) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to gnd.) in3?n6, abp, sda, scl, a0, a1, gpi1?pi4, mr , margin , po5?o8 (max6872), po3?o5 (max6873)...................-0.3v to +6v in1, po1?o4 (max6872), po1?o2 (max6873) ... -0.3v to +14v in2 ...........................................................................-20v to +20v dbp ..........................................................................-0.3v to +3v input/output current (all pins)..........................................?0ma continuous power dissipation (t a = +70?) 32-pin 7mm x 7mm thin qfn (derate 33.3mw/? above +70?) .............................2667mw operating temperature range ...........................-40? to +85? maximum junction temperature .....................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter sym b o l conditions min typ max units v in1 voltage on in1 to ensure the device is fully operational, in3?n6 = gnd 4.0 13.2 operating voltage range (note 3) v in3 to v in6 voltage on any one of in3?n6 to ensure the device is fully operational, in1 = gnd 2.7 5.5 v in1 supply voltage (note 3) v in1p minimum voltage on in1 to guarantee that the device is powered through in1 6.5 v undervoltage lockout v uvlo minimum voltage on one of in3?n6 to guarantee the device is eeprom configured. 2.5 v v in1 = +13.2v, in2?n6 = gnd, no load 1.2 1.5 ma supply current i cc writing to configuration registers or eeprom, no load 1.3 2 ma v in1 (50mv increments) 2.5 13.2 v in1 (25mv increments) 1.250 7.625 v in2 (50mv increments) ?.50 ?5.25 v in2 (25mv increments) ?.250 ?.625 v in3 ? in6 (20mv increments) 1.0 5.5 threshold range v th v in3 ? in6 (10mv increments) 0.50 3.05 v t a = +25? -1.0 +1.0 in1?n6 positive, v in_ falling t a = -40? to +85? -1.5 +1.5 t a = +25? -1.5 +1.5 -15.25v v in2 -5v, v in2 falling t a = -40? to +85? -2 +2 % t a = +25? -75 +75 threshold accuracy -5v v in2 0, v in2 falling t a = -40? to +85? -100 +100 mv threshold hysteresis v th-hyst 0.3 % v th reset threshold temperature coefficient ? v th /? 10 ppm/ ? threshold-voltage differential nonlinearity v th dnl -1 +1 lsb
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units in1 input leakage current i lin1 for v in1 < the highest of v in3 ? in6 100 140 ? in2 input impedance r in2 160 230 320 k ? in3?n6 input impedance r in3 to r in6 v in1 > 6.5v 70 100 145 k ? power-up delay t pu v abp v uvlo 3.5 ms in_ to po_ delay t dpo v in_ falling or rising, 100mv overdrive 25 ? 000 25 ? 001 1.406 1.5625 1.719 010 5.625 6.25 6.875 011 22.5 25 27.5 100 45 50 55 101 180 200 220 110 360 400 440 po_ timeout period t rp register contents (table 23) 111 1440 1600 1760 ms v abp +2.5v, i sink = 500? 0.3 po1?o4 (max6872), po1?o2 (max6873) output low (note 3) v ol v abp +4.0v, i sink = 2ma 0.4 v v abp +2.5v, i sink = 1ma 0.3 po5?o8 (max6872), po3?o5 (max6873) output low (note 3) v ol v abp +4.0v, i sink = 4ma 0.4 v po1?o8 output initial pulldown current i pd v abp v uvlo , v po_ = 0.8v 10 40 ? po1?o8 output open-drain leakage current i lkg output high impedance -1 +1 ? po1?o8 output pullup resistance, weak pullup selected r pu v po_ = 2v 6.6 10 15 k ? () () ( ) = = + = + () () = = + = + () () ( ) +2.7v, i source = 10ma, output pulled up to the same in_ 1.5 any one of v in3 ? in6 +2.7v, i source = 1ma, output pulled up to the same in_ 0.8 x v in_ po5?o8 (max6872), po3?o5 (max6873) output high, push-pull selected (note 3) v oh any one of v in3 ? in6 +4.5v, i source = 2ma, output pulled up to the same in_ 0.8 x v in_ v electrical characteristics (continued) (v in1 = +6.5v to +13.2v, v in2 = +10v, v in3 ? in6 = +2.7v to +5.5v, gpi_ = gnd, margin = mr = dbp, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (notes 1, 2)
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors 4 _______________________________________________________________________________________ parameter sym b o l conditions min typ max units v il 0.8 mr , margin , gpi_ input voltage v ih 1.4 v mr input pulse width t mr 1s mr glitch rejection 100 ns mr to po_ delay t dmr 2s mr to v dbp pullup current i mr v mr = +1.4v 5 10 15 a margin to v dbp pullup current i margin v margin = +1.4v 5 10 15 a gpi_ to po_ delay t dgpi_ 200 ns gpi_ pulldown current i gpi_ v gpi_ = +0.8v 5 10 15 a watchdog input pulse width t wdi gpi_ configured as a watchdog input 50 ns 000 5.625 6.25 6.875 001 22.5 25 27.5 010 90 100 110 011 360 400 440 ms 100 1.44 1.6 1.76 101 5.76 6.4 7.04 110 23.04 25.6 28.16 watchdog timeout period t wd register contents (table 26) 111 92.16 102.4 112.64 s serial interface logic (sda, scl, a0, a1) logic input low voltage v il 0.8 v logic input high voltage v ih 2.0 v input leakage current i lkg -1 +1 ? output voltage low v ol i sink = 3ma 0.4 v input/output capacitance c i/o 10 pf electrical characteristics (continued) (v in1 = +6.5v to +13.2v, v in2 = +10v, v in3 ? in6 = +2.7v to +5.5v, gpi_ = gnd, margin = mr = dbp, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (notes 1, 2)
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors _______________________________________________________________________________________ 5 note 1: specifications guaranteed for the stated global conditions. the device also meets the parameters specified when 0 < v in1 < +6.5v, and at least one of v in3 through v in6 is between +2.7v and +5.5v, while the remaining v in3 through v in6 are between 0 and +5.5v. note 2: device may be supplied from any one of in_, except in2. note 3: the internal supply voltage, measured at abp, equals the maximum of in3?n6 if v in1 = 0, or equals +5.4v if v in1 > +6.5v. for +4v < v in1 < +6.5v and v in3 through v in6 > +2.7v, the input that powers the device cannot be determined. note 4: 100% production tested at t a = +25? and t a = +85?. specifications at t a = -40? are guaranteed by design. note 5: c bus = total capacitance of one bus line in pf. rise and fall times are measured between 0.1 x v bus and 0.9 x v bus . note 6: input filters on sda, scl, a0, and a1 suppress noise spikes < 50ns. note 7: an additional cycle is required when writing to configuration memory for the first time. timing characteristics (in1 = gnd, v in2 = +10v, v in3 ? in6 = +2.7v to +5.5v, gpi_ = gnd, margin = mr = dbp, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (notes 1, 2) parameter sym b o l conditions min typ max units timing characteristics (figure 2) serial clock frequency f scl 400 khz clock low period t low 1.3 ? clock high period t high 0.6 ? bus-free time t buf 1.3 ? start setup time t su:sta 0.6 ? start hold time t hd:sta 0.6 ? stop setup time t su:sto 0.6 ? data-in setup time t su:dat 100 ns data-in hold time t hd:dat 0 900 ns receive scl/sda minimum rise time t r (note 5) 20 + 0.1 x c bus ns receive scl/sda maximum rise time t r (note 5) 300 ns receive scl/sda minimum fall time t f (note 5) 20 + 0.1 x c bus ns receive scl/sda maximum fall time t f (note 5) 300 ns transmit sda fall time t f c bus = 400pf 20 + 0.1 x c bus 300 ns pulse width of spike suppressed t sp (note 6) 50 ns eeprom byte write cycle time t wr (note 7) 11 ms
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors 6 _______________________________________________________________________________________ typical operating characteristics (v in1 = +6.5v to +13.2v, v in2 = +10v, v in3 ? in6 = +2.7v to +5.5v, gpi_ = gnd, margin = mr = dbp, t a = +25?, unless other- wise noted.) supply current vs. supply voltage (in1) max6872/73 toc01 supply voltage (v) supply current (ma) 12.5 11.5 10.5 9.5 8.5 7.5 0.9 1.0 1.1 1.2 1.3 1.4 1.5 0.8 6.5 13.5 t a = +85 c t a = +25 c t a = -40 c supply current vs. supply voltage (in3?n6) max6872/73 toc02 supply voltage (v) supply current (ma) 5.0 4.5 4.0 3.5 3.0 0.9 1.0 1.1 1.2 1.3 1.4 1.5 0.8 2.5 5.5 t a = +25 c t a = +85 c t a = -40 c normalized po_ timeout period vs. temperature max6872/73 toc03 temperature ( c) normalized po_ timeout period 60 35 -15 10 0.97 0.98 0.99 1.00 1.02 1.01 1.03 1.04 0.96 -40 85 in_ to po_ propagation delay vs. temperature max6872/73 toc04 temperature ( c) in_ to po_ output propagation delay ( s) 60 35 10 -15 12 14 16 18 20 22 24 26 28 30 10 -40 85 100mv overdrive normalized watchdog timeout period vs. temperature max6872/73 toc05 temperature ( c) normalized watchdog timeout period 60 35 -15 10 0.985 0.990 0.995 1.000 1.010 1.005 1.015 1.020 0.980 -40 85 normalized in_ threshold vs. temperature max6872/73 toc06 temperature ( c) normalized in_ threshold 60 35 10 -15 0.992 0.994 0.996 0.998 1.000 1.002 1.004 1.006 1.008 1.010 0.990 -40 85 in3 threshold = 1v, 20mv/step range maximum in_ transient duration vs. in_ threshold overdrive max6872/73 toc07 in_ threshold overdrive (mv) maximum in_ transient duration ( s) 100 10 10 20 30 40 50 60 70 80 90 100 110 120 130 0 1 1000 po_ assertion occurs above this line output voltage low vs. sink current max6872/73 toc08 i sink (ma) v ol (mv) 13 12 10 11 3 4 56789 1 2 50 100 150 200 250 300 350 400 450 0 014 15 open-drain, charge pump, or weak pullup po1?o4 (max6872) po1?o2 (max6873) push-pull po5?o8 (max6872) po3?o5 (max6873)
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors _______________________________________________________________________________________ 7 output voltage high vs. source current (push-pull output) max6872/73 toc10 i out (ma) v oh (v) 55 50 40 45 10 15 20 25 30 35 5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 060 push-pull to in3 in3 = 5v po5?o8 (max6872) po3?o5 (max6873) output voltage high vs. source current (charge-pump output) max6872/73 toc11 i out ( a) v oh (v) 4 3 2 1 3.5 4.0 4.5 5.0 5.5 6.0 3.0 05 measured relative to v abp po1?o4 (max6872) po1?o2 (max6873) mr to po_ propagation delay vs. temperature max6872/73 toc12 temperature ( c) mr to po_ propagation delay ( s) 60 35 -15 10 1.55 1.60 1.65 1.70 1.80 1.75 1.85 1.90 1.50 -40 85 maximum mr transient duration vs. mr threshold overdrive max6872/73 toc13 mr threshold overdrive (mv) maximum mr transient duration ( s) 100 10 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 1 1000 po_ assertion occurs above this line output voltage high vs. source current (weak pullup output) max6872/73 toc09 i out (ma) v oh (v) 4.5 4.0 3.0 3.5 1.0 1.5 2.0 2.5 0.5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 05.0 weak pullup to abp typical operating characteristics (continued) (v in1 = +6.5v to +13.2v, v in2 = +10v, v in3 ? in6 = +2.7v to +5.5v, gpi_ = gnd, margin = mr = dbp, t a = +25?, unless other- wise noted.) fet (irf7811w) turn-on with charge pump max6872/73 toc14 10ms/div v po1 10v/div v source 2v/div i drain 5a/div see figure 9
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors 8 _______________________________________________________________________________________ pin description pin max6872 max6873 name function 1 3 po2 programmable output 2. configurable, active-high, active-low, open-drain, weak pullup, or charge-pump output. po2 pulls low with a 10? internal current sink for 1v < v abp < v uvlo . po2 assumes its programmed conditional output state when abp exceeds uvlo. 2 5 po3 programmable output 3. configurable, active-high, active-low, open-drain, weak pullup (max6872), push-pull (max6873), or charge-pump (max6872) output. po3 pulls low with a 10? internal current sink for 1v < v abp < v uvlo . po3 assumes its programmed conditional output state when abp exceeds uvlo. 3 6 po4 programmable output 4. configurable, active-high, active-low, open-drain, weak pullup (max6872), push-pull (max6873), or charge-pump (max6872) output. po4 pulls low with a 10? internal current sink for 1v < v abp < v uvlo . po4 assumes its programmed conditional output state when abp exceeds uvlo. 4 4 gnd ground 5 7 po5 programmable output 5. configurable, active-high, active-low, open-drain, weak pullup, or push-pull output. po5 pulls low with a 10? internal current sink for 1v < v abp < v uvlo . po5 assumes its programmed conditional output state when abp exceeds uvlo. 6 po6 programmable output 6. configurable, active-high, active-low, open-drain, weak pullup, or push-pull output. po6 pulls low with a 10? internal current sink for 1v < v abp < v uvlo . po6 assumes its programmed conditional output state when abp exceeds uvlo. 7 po7 programmable output 7. configurable, active-high, active-low, open-drain, weak pullup, or push-pull output. po7 pulls low with a 10? internal current sink for 1v < v abp < v uvlo . po7 assumes its programmed conditional output state when abp exceeds uvlo. 8 po8 programmable output 8. configurable, active-high, active-low, open-drain, weak pullup, or push-pull output. po8 pulls low with a 10? internal current sink for 1v < v abp < v uvlo . po8 assumes its programmed conditional output state when abp exceeds uvlo. 9, 10, 23, 24 1, 8, 9, 10, 23?6, 32 n.c. no connection. not internally connected. 11 11 margin margin input. configure margin to either assert po_ into a programmed state or to hold po_ in its existing state when driving margin low (see table 7). leave margin unconnected or connect to dbp if unused. margin overrides mr if both assert at the same time. margin is internally pulled up to dbp through a 10? current source. 12 12 mr manual reset input. configure mr to either assert po_ into a programmed state or to have no effect on po_ when driving mr low (see table 6). leave mr unconnected or connect to dbp if unused. mr is internally pulled up to dbp through a 10? current source. 13 13 sda serial data input/output (open-drain). sda requires an external pullup resistor. 14 14 scl serial clock input. scl requires an external pullup resistor. 15 15 a0 address input 0. address inputs allow up to four max6872/max6873 connections on one common bus. connect a0 to gnd or to the serial interface power supply. 16 16 a1 address input 1. address inputs allow up to four max6872/max6873 connections on one common bus. connect a1 to gnd or to the serial interface power supply.
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors _______________________________________________________________________________________ 9 pin description (continued) pin max6872 max6873 name function 17 17 gpi4 general-purpose logic input 4. an internal 10? current source pulls gpi4 to gnd. configure gpi4 to control watchdog timer functions or the programmable outputs. 18 18 gpi3 general-purpose logic input 3. an internal 10? current source pulls gpi3 to gnd. configure gpi3 to control watchdog timer functions or the programmable outputs. 19 19 gpi2 general-purpose logic input 2. an internal 10? current source pulls gpi2 to gnd. configure gpi2 to control watchdog timer functions or the programmable outputs. 20 20 gpi1 general-purpose logic input 1. an internal 10? current source pulls gpi1 to gnd. configure gpi1 to control watchdog timer functions or the programmable outputs. 21 21 abp internal power-supply output. bypass abp to gnd with a 1? ceramic capacitor. abp powers the internal circuitry of the max6872/max6873. abp supplies the input voltage to the internal charge pumps when the programmable outputs are configured as charge- pump outputs. do not use abp to supply power to external circuitry. 22 22 dbp internal digital power-supply output. bypass dbp to gnd with a 1? ceramic capacitor. dbp supplies power to the eeprom memory and the internal logic circuitry. do not use dbp to supply power to external circuitry. 25 in6 voltage input 6. configure in6 to detect voltage thresholds between 1v and 5.5v in 20mv increments, or 0.5v to 3.05v in 10mv increments. for improved noise immunity, bypass in6 to gnd with a 0.1? capacitor installed as close to the device as possible. 26 in5 voltage input 5. configure in5 to detect voltage thresholds between 1v and 5.5v in 20mv increments, or 0.5v to 3.05v in 10mv increments. for improved noise immunity, bypass in5 to gnd with a 0.1? capacitor installed as close to the device as possible. 27 27 in4 voltage input 4. configure in4 to detect voltage thresholds between 1v and 5.5v in 20mv increments, or 0.5v to 3.05v in 10mv increments. for improved noise immunity, bypass in4 to gnd with a 0.1? capacitor installed as close to the device as possible. 28 28 in3 voltage input 3. configure in3 to detect voltage thresholds between 1v and 5.5v in 20mv increments, or 0.5v to 3.05v in 10mv increments. for improved noise immunity, bypass in3 to gnd with a 0.1? capacitor installed as close to the device as possible. 29 29 in2 bipolar voltage input 2. configure in2 to detect negative voltage thresholds from -2.5v to -15.25v in 50mv increments or -1.25v to -7.625v in 25mv increments. alternatively, configure in2 to detect positive voltage thresholds from 2.5v to 15.25v in 50mv increments or 1.25v to 7.625v in 25mv increments. for improved noise immunity, bypass in2 to gnd with a 0.1? capacitor installed as close to the device as possible. 30 30 in1 high-voltage input 1. configure in1 to detect voltage thresholds from 2.5v to 13.2v in 50mv increments or 1.25v to 7.625v in 25mv increments. for improved noise immunity, bypass in1 to gnd with a 0.1? capacitor installed as close to the device as possible. 31 31 i.c. internal connection. leave unconnected. 32 2 po1 programmable output 1. configurable active-high, active-low, open-drain, weak pullup, or charge-pump output. po1 pulls low with a weak 10? internal current sink for 1v < v abp < v uvlo . po1 assumes its programmed conditional output state when abp exceeds uvlo. ep exposed paddle. exposed paddle is internally connected to gnd.
max6872/max6873 detailed description the max6872/max6873 eeprom-configurable, multi- voltage supply sequencers/supervisors monitor several voltage-detector inputs and four general-purpose logic inputs, and feature programmable outputs for highly configurable, power-supply sequencing applications. the max6872 features six voltage-detector inputs and eight programmable outputs, while the max6873 fea- tures four voltage-detector inputs and five programma- ble outputs. manual reset and margin disable inputs simplify board-level testing during the manufacturing process. the max6872/max6873 feature an accurate internal 1.25v reference. all voltage detectors provide two configurable thresh- olds for undervoltage/overvoltage or dual undervoltage detection. one high-voltage input (in1) provides detec- tor threshold voltages from +1.25v to +7.625v in 25mv increments or +2.5v to +13.2v in 50mv increments. a bipolar input (in2) provides detector threshold volt- ages from ?.25v to ?.625v in 25mv increments, or ?.5v to ?5.25v in 50mv increments. positive inputs (in3?n6) provide detector threshold voltages from +0.5v to +3.05v in 10mv increments, or +1.0v to +5.5v in 20mv increments. the host controller communicates with the max6872/ max6873s?internal 4kb user eeprom, configuration eeprom, configuration registers, and fault registers through an smbus/i 2 c-compatible serial interface (see figure 1). programmable output options include active-high, active-low, open-drain, weak pullup, push-pull, and charge pump. select the charge-pump output feature to drive n-channel fets for power-supply sequencing (see the applications information section). the outputs swing between 0 and (v abp + 5v) when configured for charge-pump operation. eeprom-programmable, hex/quad, power-supply sequencers/supervisors 10 ______________________________________________________________________________________ comparators register bank controller eeprom (user and config) output stages logic network for po_ watchdog timers gpi_ gpi_, mr, margin po_ in_ sda, scl analog block digital block serial interface figure 1. top-level block diagram
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 11 max6872 max6873 1.25v v ref in2 detector in_ detector in1 in2 in3 in4 in5 (n.c.) in6 (n.c.) in3 detector in4 detector in5 detector in6 detector programmable array timing block 2 timing block 3 timing block 4 timing block 5 timing block 6 timing block 7 timing block 8 po2 output po3 output po4 output po5 output po6 output po7 output po8 output timing block 1 v abp + 5v charge pump* mux gpi1 gpi2 gpi3 gpi4 margin mr in3?n6 (in3?n4) po_ output *po1?o4 only (po1, po2) abp mux p1** 10k ? po1 po2 po3 po4 po5 po6 (n.c.) po7 (n.c.) po8 (n.c.) open- drain ** po5?o8 only (po3, po4, po5) main oscillator serial interface sda scl a0 a1 eeprom charge pump config registers config eeprom user eeprom 1 f abp dbp 1 f 2.55v ldo 5.4v ldo (virtual diodes) gnd ( ) are for max6873 only. functional diagram
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors 12 ______________________________________________________________________________________ program each output to assert on any voltage-detector input, general-purpose logic input, watchdog timer, manual reset, or other output stages. programmable timing-delay blocks configure each output to wait between 25? and 1600ms before deasserting. a fault register logs the conditions that caused each output to assert (undervoltage, overvoltage, manual reset, etc.). the max6872/max6873 feature two watchdog timers, adding flexibility. program each watchdog timer to assert one or more programmable outputs. program each watchdog timer to clear on a combination of one gpi_ input and one programmable output, one of the gpi_ inputs only, or one of the programmable outputs only. the initial and normal watchdog timeout periods are independently programmable from 6.25ms to 102.4s. a virtual diode-oring scheme selects the input that pow- ers the max6872/max6873. the max6872/max6873 derive power from in1 if v in1 > +6.5v or from the highest voltage on in3?n6 if v in1 < +2.7v. the power source cannot be determined if +4v < v in1 < +6.5v and one of v in3 through v in6 > +2.7v. the programmable out- puts maintain the correct programmed logic state for v abp > v uvlo . one of in3 through in6 must be greater than +2.7v or in1 must be greater than +4v for device operation. powering the max6872/max6873 the max6872/max6873 derive power from the positive voltage-detector inputs: in1 or in3?n6. a virtual diode- oring scheme selects the positive input that supplies power to the device (see the functional diagram ). in1 must be at least +4v or one of in3?n6 (max6872)/ in3?n4 (max6873) must be at least +2.7v to ensure device operation. an internal ldo regulates in1 down to +5.4v. the highest input voltage on in3?n6 (max6872)/ in3?n4 (max6873) supplies power to the device, unless v in1 +6.5v, in which case in1 supplies power to the device. for +4v < v in1 < +6.5v and one of v in3 through v in6 > +2.7v, the input power source cannot be deter- mined due to the dropout voltage of the ldo. internal hysteresis ensures that the supply input that initially pow- ered the device continues to power the device when multiple input voltages are within 50mv of each other. abp powers the analog circuitry; bypass abp to gnd with a 1? ceramic capacitor installed as close to the device as possible. the internal supply voltage, mea- sured at abp, equals the maximum of in3?n6 (max6872)/in3?n4 (max6873) if v in1 = 0, or equals +5.4v when v in1 > +6.5v. do not use abp to provide power to external circuitry. the max6872/max6873 also generate a digital supply voltage (dbp) for the internal logic circuitry and the eeprom; bypass dbp to gnd with a 1? ceramic capacitor installed as close to the device as possible. the nominal dbp output voltage is +2.55v. do not use dbp to provide power to external circuitry. inputs the max6872/max6873 contain multiple logic and volt- age-detector inputs. each voltage-detector input is simultaneously monitored for primary and secondary thresholds. the primary threshold must be an under- voltage threshold. the secondary threshold may be an undervoltage or overvoltage threshold. table 1 summa- rizes these various inputs. set the primary and secondary threshold voltages for each voltage-detector input with registers 00h?bh. each primary threshold voltage must be an undervolt- age threshold. configure each secondary threshold voltage as an undervoltage or overvoltage threshold (see register 0ch). set the threshold range for each voltage detector with register 0dh. high-voltage input (in1) in1 offers threshold voltages of +2.5v to +13.2v in 50mv increments, or +1.25v to +7.625v in 25mv incre- ments. use the following equations to set the threshold voltages for in1: where v th is the desired threshold voltage and x is the decimal code for the desired threshold ( table 2). for the +2.5v to +13.2v range, x must equal 214 or less, otherwise the threshold exceeds the maximum operat- ing voltage of in1. bipolar-voltage input (in2) in2 offers negative thresholds from -2.5v to -15.25v in 50mv increments, or from -1.25v to -7.625v in 25mv increments. alternatively, in2 offers positive thresholds from +2.5v to +15.25v in 50mv increments, or +1.25v to +7.625v in 25mv increments. use the following equations to set the threshold voltages for in2: x vv v for v to v range th = () ? ?? ? . . . . 25 005 2 5 15 25 x vv v for v to v range th =++ ? . . . . 125 0 025 1 25 7 625 x vv v for v to v range th =++ ? . . . . 25 005 2 5 13 2
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 13 table 1. programmable features feature description high-voltage input (in1) ? primary undervoltage threshold ? secondary overvoltage or undervoltage threshold ? +2.5v to +13.2v threshold in 50mv increments ? +1.25v to +7.625v threshold in 25mv increments bipolar-voltage input (in2) ? primary undervoltage threshold ? secondary overvoltage or undervoltage threshold ? ?.5v to ?5.25v threshold in 50mv increments ? ?.25v to ?.625v threshold in 25mv increments positive-voltage input in3?n6 (max6872), in3?n4 (max6873) ? primary undervoltage threshold ? secondary overvoltage or undervoltage threshold ? +1v to +5.5v threshold in 20mv increments ? +0.5v to +3.05v threshold in 10mv increments programmable outputs po1?o4 (max6872), po1?o2 (max6873) ? active high or active low ? open-drain, weak pullup, or charge-pump output ? weak pullup to in3?n6 (in3 or in4 for max6873) or abp ? dependent on mr , margin , in_, gpi1?pi4 , wd1 and wd2, and/or po_ ? programmable timeout periods of 25?, 1.5625ms, 6.25ms, 25ms, 50ms, 200ms, 400ms, or 1.6s programmable outputs po5?o8 (max6872), po3?o5 (max6873) ? active high or active low ? open-drain, weak pullup, or push-pull output ? weak pullup to in3?n6 (in3 or in4 for max6873) or abp ? push-pull to in3?n6 (in3 or in4 for max6873) ? dependent on mr , margin , in_, gpi1?pi4 , wd1 and wd2, and/or po_ ? programmable timeout periods of 25?, 1.5625ms, 6.25ms, 25ms, 50ms, 200ms, 400ms, or 1.6s general-purpose logic inputs (gpi1?pi4) ? active high or active low logic levels ? configure gpi_ as inputs to watchdog timers or programmable output stages watchdog timers ? clear dependent on any combination of one gpi_ input and one programmable output, a gpi_ input only, or a programmable output only ? initial watchdog timeout period of 6.25ms, 25ms, 100ms, 400ms, 1.6s, 6.4s, 25.6s, or 102.4s ? normal watchdog timeout period of 6.25ms, 25ms, 100ms, 400ms, 1.6s, 6.4s, 25.6s, or 102.4s ? watchdog enable/disable ? initial watchdog timeout period enable/disable manual reset input ( mr ) ? forces po_ into the active output state when mr = gnd ? po_ deassert after mr releases high and the po_ timeout period expires ? po_ cannot be a function of mr only margining input ( margin ) ? holds po_ in existing state or asserts po_ to a programmed output state, independent of changes in monitored inputs or watchdog timers, when margin = gnd ? overrides mr when both assert at the same time write disable ? locks user eeprom based on po_ configuration lock ? locks configuration eeprom
where v th is the desired threshold voltage and x is the decimal code for the desired threshold ( table 3). in3?n6 in3?n6 offer positive voltage detectors monitor volt- ages from +1v to +5.5v in 20mv increments, or +0.5v to +3.05v in 10mv increments. use the following equa- tions to set the threshold voltages for in_: where v th is the desired threshold voltage and x is the decimal code for the desired threshold ( table 4). for the +1v to +5.5v range, x must equal 225 or less, oth- x vv v for v to v range th =++ ? . . . . 05 001 05 305 x vv v for v to v range th =++ ? . . 1 002 155 x vv v for v to v range th =++ ? . . . . 125 0 025 1 25 7 625 x vv v for v to v range th =++ ? . . . . 25 005 2 5 15 25 x vv v for v to v range th = () ?? ?? . . . . 125 0 025 1 25 7 625 max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors 14 ______________________________________________________________________________________ table 3. in2 threshold settings register address eeprom memory address bit range description 01h 8001h [7:0] in2 primary undervoltage detector threshold (v2a) (see equations in the bipolar-voltage input (in2) section). 07h 8007h [7:0] in2 secondary undervoltage/overvoltage detector threshold (v2b) (see equations in the bipolar-voltage input (in2) section). 0ch 800ch [1] in2 secondary overvoltage/undervoltage selection: 0 = overvoltage threshold. 1 = undervoltage threshold. 0dh 800dh [7:6] in2 range selection: 00 = -2.5v to -15.25v range in 50mv increments. 01 = -1.25v to -7.625v range in 25mv increments. 10 = +2.5v to +15.25v range in 50mv increments. 11 = +1.25v to +7.625v range in 25mv increments. table 2. in1 threshold settings register address eeprom memory address bit range description 00h 8000h [7:0] in1 primary undervoltage detector threshold (v1a) (see equations in the high-voltage input (in1) section). 06h 8006h [7:0] in1 secondary undervoltage/overvoltage detector threshold (v1b) (see equations in the high-voltage input (in1) section). 0ch 800ch [0] in1 secondary overvoltage/undervoltage selection: 0 = overvoltage threshold. 1 = undervoltage threshold. 0dh 800dh [0] in 1 r ang e sel ecti on: 0 = 2.5v to 13.2v r ang e i n 50m v i ncr em ents. 1 = 1.25v to 7.625v r ang e i n 25m v i ncr em ents.
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 15 table 4. in3?n6 threshold settings register address eeprom memory address bit range description 02h 8002h [7:0] in3 primary undervoltage detector threshold (v3a) (see equations in the in3?n6 section). 03h 8003h [7:0] in4 primary undervoltage detector threshold (v4a) (see equations in the in3?n6 section). 04h 8004h [7:0] in5 (max6872 only) primary undervoltage detector threshold (v5a) (see equations in the in3?n6 section). 05h 8005h [7:0] in6 (max6872 only) primary undervoltage detector threshold (v6a) (see equations in the in3?n6 section). 08h 8008h [7:0] in3 secondary undervoltage/overvoltage detector threshold (v3b) (see equations in the in3?n6 section). 09h 8009h [7:0] in4 secondary undervoltage/overvoltage detector threshold (v4b) (see equations in the in3?n6 section). 0ah 800ah [7:0] in5 (max6872 only) secondary undervoltage/overvoltage detector threshold (v5b) (see equations in the in3?n6 section). 0bh 800bh [7:0] in6 (max6872 only) secondary undervoltage/overvoltage detector threshold (v6b) (see equations in the in3?n6 section). [2] in3 secondary overvoltage/undervoltage selection. 0 = overvoltage threshold. 1 = undervoltage threshold. [3] in4 secondary overvoltage/undervoltage selection. 0 = overvoltage threshold. 1 = undervoltage threshold. [4] in5 (max6872 only) secondary overvoltage/undervoltage selection. 0 = overvoltage threshold. 1 = undervoltage threshold. [5] in6 (max6872 only) secondary overvoltage/undervoltage selection. 0 = overvoltage threshold. 1 = undervoltage threshold. 0ch 800ch [7:6] not used. [1] in 3 r ang e sel ecti on. 0 = + 1v to + 5.5v r ang e i n 20m v i ncr em ents. 1 = + 0.5v to + 3.05v r ang e i n 10m v i ncr em ents. [2] in 4 r ang e sel ecti on. 0 = + 1v to + 5.5v r ang e i n 20m v i ncr em ents. 1 = + 0.5v to + 3.05v r ang e i n 10m v i ncr em ents. [3] in 5 ( m ax 6872 onl y) r ang e sel ecti on. 0 = + 1v to + 5.5v r ang e i n 20m v i ncr em ents. 1 = + 0.5v to + 3.05v r ang e i n 10m v i ncr em ents. [4] in 6 ( m ax 6872 onl y) r ang e sel ecti on. 0 = + 1v to + 5.5v r ang e i n 20m v i ncr em ents. 1 = + 0.5v to + 3.05v r ang e i n 10m v i ncr em ents. 0dh 800dh [5] not used. erwise the threshold exceeds the maximum operating voltage of in3?n6. gpi1?pi4 the gpi1?pi4 programmable logic inputs control power-supply sequencing (programmable outputs), reset/interrupt signaling, and watchdog functions (see the configuring the watchdog timers (registers 3ch?fh) section). configure gpi1?pi4 for active-low or active-high logic ( table 5). gpi1?pi4 internally pull down to gnd through a 10? current sink.
mr the manual reset ( mr ) input initiates a reset condi- tion. register 40h determines the programmable out- puts that assert while mr is low ( table 6). all affected programmable outputs remain asserted (see the programmable outputs section) for their po_ timeout periods after mr releases high. an internal 10? cur- rent source pulls mr to dbp. leave mr unconnected or connect to dbp if unused. a programmable output cannot depend solely on mr . margin margin allows system-level testing while power sup- plies exceed the normal ranges. registers 41h and 42h determine whether the programmable outputs assert to a predetermined state or hold the last state as margin is driven low ( table 7). drive margin low to set the programmable outputs in a known state while system-level testing occurs. leave margin unconnected or connect to dbp if unused. an internal 10? current source pulls margin to dbp. the state of each programmable output does not change while margin = gnd. margin overrides mr if both assert at the same time. programmable outputs the max6872 features eight programmable outputs, while the max6873 features five programmable outputs. selectable output-stage configurations include: active low or active high, open drain, weak pullup, push-pull, or charge pump. during power-up, the programmable out- puts pull to gnd with an internal 10? current sink for 1v < v abp < v uvlo . the programmable outputs remain in their active states until their respective po_ timeout peri- ods expire, and all of the programmed conditions are met for each output. any output programmed to depend on no condition always remains in its active state ( table 20). an active-high configured output is considered asserted max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors 16 ______________________________________________________________________________________ table 5. gpi1?pi4 active logic states register address eeprom memory address bit range description [0] gpi1. 0 = active low. 1 = active high. [1] gpi2. 0 = active low. 1 = active high. [2] gpi3. 0 = active low. 1 = active high. 3bh 803bh [3] gpi4. 0 = active low. 1 = active high. table 6. programmable output behavior and mr rgir ar rm mmr ar i rang riin [0] po1 (max6872 only). 0 = po1 independent of mr . 1 = po1 asserts when mr = low. [1] po2 (max6872 only). 0 = po2 independent of mr . 1 = po2 asserts when mr = low. [2] po3 (max6872)/po1 (max6873). 0 = po3/po1 independent of mr . 1 = po3/po1 asserts when mr = low. [3] po4 (max6872)/po2 (max6873). 0 = po4/po2 independent of mr . 1 = po4/po2 asserts when mr = low. [4] po5 (max6872)/po3 (max6873). 0 = po5/po3 independent of mr . 1 = po5/po3 asserts when mr = low. [5] po6 (max6872)/po4 (max6873). 0 = po6/po4 independent of mr . 1 = po6/po4 asserts when mr = low. [6] po7 (max6872)/po5 (max6873). 0 = po7/po5 independent of mr . 1 = po7/po5 asserts when mr = low. 40h 8040h [7] po8 (max6872 only). 0 = po8 independent of mr . 1 = po8 asserts when mr = low.
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 17 when that output is logic-high. no output can depend solely on mr . the positive voltage monitors generate fault signals (logical 0) to the max6872/max6873s?logic array when an input voltage is below the programmed undervolt- age threshold, or when that voltage is above the over- voltage threshold. the negative voltage monitor (in2) generates a fault signal to the logic array when the input voltage is less negative than the undervoltage threshold, or when that voltage is more negative than the overvoltage threshold. registers 0eh through 3ah and 40h configure each of the programmable outputs. programmable timing blocks set the po_ timeout period from 25? to 1600ms table 7. programmable output behavior and margin register address eeprom memory address bit range affected output description [0] po1 (max6872 only) 0 = output held in existing state. 1 = output asserts high or low (see 42h[0]). [1] po2 (max6872 only) 0 = output held in existing state. 1 = output asserts high or low (see 42h[1]). [2] po3 (max6872) po1 (max6873) 0 = output held in existing state. 1 = output asserts high or low (see 42h[2]). [3] po4 (max6872) po2 (max6873) 0 = output held in existing state. 1 = output asserts high or low (see 42h[3]). [4] po5 (max6872) po3 (max6873) 0 = output held in existing state. 1 = output asserts high or low (see 42h[4]). [5] po6 (max6872) po4 (max6873) 0 = output held in existing state. 1 = output asserts high or low (see 42h[5]). [6] po7 (max6872) po5 (max6873) 0 = output held in existing state. 1 = output asserts high or low (see 42h[6]). 41h 8041h [7] po8 (max6872 only) 0 = output held in existing state. 1 = output asserts high or low (see 42h[7]). [0] po1 (max6872 only) 0 = output asserts low if 41h[0] = 1. 1 = output asserts high if 41h[0] = 1. [1] po2 (max6872 only) 0 = output asserts low if 41h[1] = 1. 1 = output asserts high if 41h[1] = 1. [2] po3 (max6872) po1 (max6873) 0 = output asserts low if 41h[2] = 1. 1 = output asserts high if 41h[2] = 1. [3] po4 (max6872) po2 (max6873) 0 = output asserts low if 41h[3] = 1. 1 = output asserts high if 41h[3] = 1. [4] po5 (max6872) po3 (max6873) 0 = output asserts low if 41h[4] = 1. 1 = output asserts high if 41h[4] = 1. [5] po6 (max6872) po4 (max6873) 0 = output asserts low if 41h[5] = 1. 1 = output asserts high if 41h[5] = 1. [6] po7 (max6872) po5 (max6873) 0 = output asserts low if 41h[6] = 1. 1 = output asserts high if 41h[6] = 1. 42h 8042h [7] po8 (max6872 only) 0 = output asserts low if 41h[7] = 1. 1 = output asserts high if 41h[7] = 1.
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors 18 ______________________________________________________________________________________ table 8. po1 (max6872 only) output dependency register address eeprom memory address bit output assertion conditions [0] 1 = po1 assertion depends on in1 primary undervoltage threshold (table 2). [1] 1 = po1 assertion depends on in2 primary undervoltage threshold (table 3). [2] 1 = po1 assertion depends on in3 primary undervoltage threshold (table 4). [3] 1 = po1 assertion depends on in4 primary undervoltage threshold (table 4). [4] 1 = po1 assertion depends on in5 primary undervoltage threshold (table 4). [5] 1 = po1 assertion depends on in6 primary undervoltage threshold (table 4). [6] 1 = po1 assertion depends on watchdog 1 (tables 25 and 26). 0eh 800eh [7] 1 = po1 assertion depends on watchdog 2 (tables 25 and 26). [0] 1 = p o1 asser ti on d ep end s on in 1 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 2) . [1] 1 = p o1 asser ti on d ep end s on in 2 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 3) . [2] 1 = p o1 asser ti on d ep end s on in 3 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [3] 1 = p o1 asser ti on d ep end s on in 4 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [4] 1 = p o1 asser ti on d ep end s on in 5 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [5] 1 = p o1 asser ti on d ep end s on in 6 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [6] 1 = po1 assertion depends on gpi1 (table 5). 0fh 800fh [7] 1 = po1 assertion depends on gpi2 (table 5). [0] 1 = po1 assertion depends on gpi3 (table 5). [1] 1 = po1 assertion depends on gpi4 (table 5). [2] 1 = po1 assertion depends on po2 (table 9). [3] 1 = po1 assertion depends on po3 (tables 10 and 11). [4] 1 = po1 assertion depends on po4 (tables 12 and 13). [5] 1 = po1 assertion depends on po5 (tables 14 and 15). [6] 1 = po1 assertion depends on po6 (tables 16 and 17). 10h 8010h [7] 1 = po1 assertion depends on po7 (table 18). 11h 8011h [0] 1 = po1 assertion depends on po8 (table 19). 40h 8040h [0] 1 = po1 asserts when mr = low (table 6). for each programmable output. see register 3ah ( table 20) to set the active state (active-high or active-low) for each programmable output and registers 11h, 15h, 1ch, 23h, 2ah, 31h, 35h, and 39h to select the output stage types (tables 21 and 22), and po_ timeout peri- ods ( table 23) for each output. control selected programmable outputs with a sum of products (tables 8?9). each product allows a different set of conditions to assert each output. outputs po3 (max6872)/po1 (max6873) and po6 (max6872)/ po4 (max6873) allow two sets of different conditions to assert each output. outputs po1 and po2 (max6872 only), po7 (max6872)/po5 (max6873), and po8 (max6872 only) allow only one set of conditions to assert each output. for example, product 1 of the po3 (max6872 table 10) programmable output may depend on the in1 pri- mary undervoltage threshold, and the states of gpi1, po1, and po2. write a one to r16h[0], r17h[6], and r18h[3:2] to configure product 1 as indicated. in1 must be above the primary undervoltage threshold ( table 2), gpi1 must be inactive ( table 5), and po1 (tables 8 and 20) and po2 (tables 10 and 21) must be in their deasserted states for product 1 to be a logi- cal 1. product 1 is equivalent to the logic statement: v1a ? gpi1 ? po1 ? po2. product 2 of po3 (max6872, table 11) may depend on an entirely different set of conditions, or the same condi- tions, depending on the system requirements. for example, product 2 may depend on the in1 undervolt-
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 19 age threshold, and the states of gpi2 and wd1. write ones to r19h[6, 0] and r1ah[7] to configure product 2 as indicated. in1 must be above the primary undervolt- age threshold ( table 2), gpi2 must be inactive ( table 5), and the wd1 timer must not have expired (tables 25 and 26) for product 2 to be a logical 1. product 2 is equivalent to the logic statement: v1a ? gpi2 ? wd1. po3 deasserts if either product 1 or product 2 is a logi- cal 1. the logical statement: product 1 + product 2 determines the state of po3. t able 8 only applies to po1 of the max6872. write a 0 to a bit to make the po1 output independent of the respective signal (in1?n6 primary or secondary thresholds, wd1 or wd2, gpi1?pi4, mr , or other pro- grammable outputs). t able 9 only applies to po2 of the max6872. write a 0 to a bit to make the po2 output independent of the respective signal (in1?n6 primary or secondary thresholds, wd1 or wd2, gpi1?pi4, mr , or other pro- grammable outputs). table 9. po2 (max6872 only) output dependency register address eeprom memory address bit output assertion conditions [0] 1 = po2 assertion depends on in1 primary undervoltage threshold (table 2). [1] 1 = po2 assertion depends on in2 primary undervoltage threshold (table 3). [2] 1 = po2 assertion depends on in3 primary undervoltage threshold (table 4). [3] 1 = po2 assertion depends on in4 primary undervoltage threshold (table 4). [4] 1 = po2 assertion depends on in5 primary undervoltage threshold (table 4). [5] 1 = po2 assertion depends on in6 primary undervoltage threshold (table 4). [6] 1 = po2 assertion depends on watchdog 1 (tables 25 and 26). 12h 8012h [7] 1 = po2 assertion depends on watchdog 2 (tables 25 and 26). [0] 1 = p o2 asser ti on d ep end s on in 1 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 2) . [1] 1 = p o2 asser ti on d ep end s on in 2 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 3) . [2] 1 = p o2 asser ti on d ep end s on in 3 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [3] 1 = p o2 asser ti on d ep end s on in 4 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [4] 1 = p o2 asser ti on d ep end s on in 5 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [5] 1 = p o2 asser ti on d ep end s on in 6 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [6] 1 = po2 assertion depends on gpi1 (table 5). 13h 8013h [7] 1 = po2 assertion depends on gpi2 (table 5). [0] 1 = po2 assertion depends on gpi3 (table 5). [1] 1 = po2 assertion depends on gpi4 (table 5). [2] 1 = po2 assertion depends on po1 (table 8). [3] 1 = po2 assertion depends on po3 (tables 10 and 11). [4] 1 = po2 assertion depends on po4 (tables 12 and 13). [5] 1 = po2 assertion depends on po5 (tables 14 and 15). [6] 1 = po2 assertion depends on po6 (tables 16 and 17). 14h 8014h [7] 1 = po2 assertion depends on po7 (table 18). 15h 8015h [0] 1 = po2 assertion depends on po8 (table 19). 40h 8040h [1] 1 = po2 asserts when mr = low (table 6).
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors 20 ______________________________________________________________________________________ table 10. po3 (max6872)/po1 (max6873) output dependency (product 1) register address eeprom memory address bit output assertion conditions [0] 1 = po3/po1 assertion depends on in1 primary undervoltage threshold (table 2). [1] 1 = po3/po1 assertion depends on in2 primary undervoltage threshold (table 3). [2] 1 = po3/po1 assertion depends on in3 primary undervoltage threshold (table 4). [3] 1 = po3/po1 assertion depends on in4 primary undervoltage threshold (table 4). [4] 1 = po3 (max6872 only) assertion depends on in5 primary undervoltage threshold (table 4). must be set to 0 for the max6873. [5] 1 = po3 (max6872 only) assertion depends on in6 primary undervoltage threshold (table 4). must be set to 0 for the max6873. [6] 1 = po3/po1 assertion depends on watchdog 1 (tables 25 and 26). 16h 8016h [7] 1 = po3/po1 assertion depends on watchdog 2 (tables 25 and 26). [0] 1 = p o3/p o1 asser ti on d ep end s on in 1 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 2) . [1] 1 = p o3/p o1 asser ti on d ep end s on in 2 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 3) . [2] 1 = p o3/p o1 asser ti on d ep end s on in 3 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [3] 1 = p o3/p o1 asser ti on d ep end s on in 4 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [4] 1 = po3 (max6872 only) assertion depends on in5 secondary undervoltage/overvoltage threshold (table 4). must be set to 0 for the max6873. [5] 1 = po3 (max6872 only) assertion depends on in6 secondary undervoltage/overvoltage threshold (table 4). must be set to 0 for the max6873. [6] 1 = po3/po1 assertion depends on gpi1 (table 5). 17h 8017h [7] 1 = po3/po1 assertion depends on gpi2 (table 5). [0] 1 = po3/po1 assertion depends on gpi3 (table 5). [1] 1 = po3/po1 assertion depends on gpi4 (table 5). [2] 1 = p o3 ( m ax 6872 onl y) asser ti on d ep end s on p o1 ( tab l e 8) . m ust b e set to 0 for the m ax 6873. [3] 1 = p o3 ( m ax 6872 onl y) asser ti on d ep end s on p o2 ( tab l e 9) . m ust b e set to 0 for the m ax 6873. [4] 1 = po3/po1 assertion depends on po4 (max6872)/po2 (max6873) (tables 12 and 13). [5] 1 = p o3/p o 1 asser ti on d ep end s on p o5 ( m ax 6872) /p o 3 ( m ax 6873) ( tab l es 14 and 15) . [6] 1 = po3/po1 assertion depends on po6 (max6872)/po4 (max6873) (tables 16 and 17). 18h 8018h [7] 1 = po3/po1 assertion depends on po7 (max6872)/po5 (max6873) (table 18). 1ch 801ch [0] 1 = p o3 ( m ax 6872 onl y) asser ti on d ep end s on p o8 ( tab l e 19) . m ust b e set to 0 for the m ax 6873. 40h 8040h [2] 1 = po3/po1 asserts when mr = low (table 6). t able 10 only applies to po3 of the max6872 and po1 of the max6873. write a 0 to a bit to make the po3/po1 output independent of the respective signal (in_ primary or secondary thresholds, wd1 or wd2, gpi1?pi4, mr , or other programmable outputs). see table 11 for product 2. po3 (max6872)/po1 (max6873) deasserts when product 1 or product 2 = 1.
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 21 t able 11 only applies to po3 of the max6872 and po1 of the max6873. write a 0 to a bit to make the po3/po1 output independent of the respective signal (in_ primary or secondary thresholds, wd1 or wd2, gpi1?pi4, mr , or other programmable outputs). see table 10 for product 1. po3 (max6872)/po1 (max6873) deasserts when product 1 or product 2 = 1. table 11. po3 (max6872)/po1 (max6873) output dependency (product 2) register address eeprom memory address bit output assertion conditions [0] 1 = po3/po1 assertion depends on in1 primary undervoltage threshold (table 2). [1] 1 = po3/po1 assertion depends on in2 primary undervoltage threshold (table 3). [2] 1 = po3/po1 assertion depends on in3 primary undervoltage threshold (table 4). [3] 1 = po3/po1 assertion depends on in4 primary undervoltage threshold (table 4). [4] 1 = po3 (max6872 only) assertion depends on in5 primary undervoltage threshold (table 4). must be set to 0 for the max6873. [5] 1 = po3 (max6872 only) assertion depends on in6 primary undervoltage threshold (table 4). must be set to 0 for the max6873. [6] 1 = po3/po1 assertion depends on watchdog 1 (tables 25 and 26). 19h 8019h [7] 1 = po3/po1 assertion depends on watchdog 2 (tables 25 and 26). [0] 1 = p o3/p o1 asser ti on d ep end s on in 1 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 2) . [1] 1 = p o3/p o1 asser ti on d ep end s on in 2 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 3) . [2] 1 = p o3/p o1 asser ti on d ep end s on in 3 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [3] 1 = p o3/p o1 asser ti on d ep end s on in 4 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [4] 1 = po3 (max6872 only) assertion depends on in5 secondary undervoltage/overvoltage threshold (table 4). must be set to 0 for the max6873. [5] 1 = po3 (max6872 only) assertion depends on in6 secondary undervoltage/overvoltage threshold (table 4). must be set to 0 for the max6873. [6] 1 = po3/po1 assertion depends on gpi1 (table 5). 1ah 801ah [7] 1 = po3/po1 assertion depends on gpi2 (table 5). [0] 1 = po3/po1 assertion depends on gpi3 (table 5). [1] 1 = po3/po1 assertion depends on gpi4 (table 5). [2] 1 = p o3 ( m ax 6872 onl y) asser ti on d ep end s on p o1 ( tab l e 8) . m ust b e set to 0 for the m ax 6873. [3] 1 = p o3 ( m ax 6872 onl y) asser ti on d ep end s on p o2 ( tab l e 9) . m ust b e set to 0 for the m ax 6873. [4] 1 = p o3/p o 1 asser ti on d ep end s on p o4 ( m ax 6872) /p o 2 ( m ax 6873) ( tab l es 12 and 13) . [5] 1 = p o3/p o 1 asser ti on d ep end s on p o5 ( m ax 6872) /p o 3 ( m ax 6873) ( tab l es 14 and 15) . [6] 1 = p o3/p o 1 asser ti on d ep end s on p o6 ( m ax 6872) /p o 4 ( m ax 6873) ( tab l es 16 and 17) . 1bh 801bh [7] 1 = po3/po1 assertion depends on po7 (max6872)/po5 (max6873) (table 18). 1ch 801ch [1] 1 = p o3 ( m ax 6872 onl y) asser ti on d ep end s on p o8 ( tab l e 19) . m ust b e set to 0 for the m ax 6873. 40h 8040h [2] 1 = po3/po1 asserts when mr = low (table 6).
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors 22 ______________________________________________________________________________________ table 12. po4 (max6872)/po2 (max6873) output dependency (product 1) register address eeprom memory address bit output assertion conditions [0] 1 = po4/po2 assertion depends on in1 primary undervoltage threshold (table 2). [1] 1 = po4/po2 assertion depends on in2 primary undervoltage threshold (table 3). [2] 1 = po4/po2 assertion depends on in3 primary undervoltage threshold (table 4). [3] 1 = po4/po2 assertion depends on in4 primary undervoltage threshold (table 4). [4] 1 = p o4 ( m ax 6872 onl y) asser ti on d ep end s on in 5 p r i m ar y und er vol tag e thr eshol d ( tab l e 4) . m ust b e set to 0 for the m ax 6873. [5] 1 = p o4 ( m ax 6872 onl y) asser ti on d ep end s on in 6 p r i m ar y und er vol tag e thr eshol d ( tab l e 4) . m ust b e set to 0 for the m ax 6873. [6] 1 = po4/po2 assertion depends on watchdog 1 (tables 25 and 26). 1dh 801dh [7] 1 = po4/po2 assertion depends on watchdog 2 (tables 25 and 26). [0] 1 = p o4/p o2 asser ti on d ep end s on in 1 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 2) . [1] 1 = p o4/p o2 asser ti on d ep end s on in 2 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 3) . [2] 1 = p o4/p o2 asser ti on d ep end s on in 3 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [3] 1 = p o4/p o2 asser ti on d ep end s on in 4 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [4] 1 = po4 (max6872 only) assertion depends on in5 secondary undervoltage/overvoltage threshold (table 4). must be set to 0 for the max6873. [5] 1 = po4 (max6872 only) assertion depends on in6 secondary undervoltage/overvoltage threshold (table 4). must be set to 0 for the max6873. [6] 1 = po4/po2 assertion depends on gpi1 (table 5). 1eh 801eh [7] 1 = po4/po2 assertion depends on gpi2 (table 5). [0] 1 = po4/po2 assertion depends on gpi3 (table 5). [1] 1 = po4/po2 assertion depends on gpi4 (table 5). [2] 1 = p o4 ( m ax 6872 onl y) asser ti on d ep end s on p o1 ( tab l e 8) . m ust b e set to 0 for the m ax 6873. [3] 1 = p o4 ( m ax 6872 onl y) asser ti on d ep end s on p o2 ( tab l e 9) . m ust b e set to 0 for the m ax 6873. [4] 1 = p o4/p o 2 asser ti on d ep end s on p o3 ( m ax 6872) /p o 1 ( m ax 6873) ( tab l es 10 and 11) . [5] 1 = p o4/p o 2 asser ti on d ep end s on p o5 ( m ax 6872) /p o 3 ( m ax 6873) ( tab l es 14 and 15) . [6] 1 = p o4/p o 2 asser ti on d ep end s on p o6 ( m ax 6872) /p o 4 ( m ax 6873) ( tab l es 16 and 17) . 1fh 801fh [7] 1 = po4/po2 assertion depends on po7 (max6872)/po5 (max6873) (table 18). 23h 8023h [0] 1 = p o4 ( m ax 6872 onl y) asser ti on d ep end s on p o8 ( tab l e 19) . m ust b e set to 0 for the m ax 6873. 40h 8040h [3] 1 = po4/po2 asserts when mr = low (table 6). t able 12 only applies to po4 of the max6872 and po2 of the max6873. write a 0 to a bit to make the po4/po2 output independent of the respective signal (in_ primary or secondary thresholds, wd1 or wd2, gpi1?pi4, mr , or other programmable outputs). see table 13 for product 2. po4 (max6872)/po2 (max6873) deasserts when product 1 or product 2 = 1.
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 23 t able 13 only applies to po4 of the max6872 and po2 of the max6873. write a 0 to a bit to make the po4/po2 output independent of the respective signal (in_ primary or secondary thresholds, wd1 or wd2, gpi1 to gpi4, mr , or other programmable outputs). see table 12 for product 1. po4 (max6872)/po2 (max6873) deasserts when product 1 or product 2 = 1. table 13. po4 (max6872)/po2 (max6873) output dependency (product 2) register address eeprom memory address bit output assertion conditions [0] 1 = po4/po2 assertion depends on in1 primary undervoltage threshold (table 2). [1] 1 = po4/po2 assertion depends on in2 primary undervoltage threshold (table 3). [2] 1 = po4/po2 assertion depends on in3 primary undervoltage threshold (table 4). [3] 1 = po4/po2 assertion depends on in4 primary undervoltage threshold (table 4). [4] 1 = po4 (max6872 only) assertion depends on in5 primary undervoltage threshold (table 4). must be set to 0 for the max6873. [5] 1 = po4 (max6872 only) assertion depends on in6 primary undervoltage threshold (table 4). must be set to 0 for the max6873. [6] 1 = po4/po2 assertion depends on watchdog 1 (tables 25 and 26). 20h 8020h [7] 1 = po4/po2 assertion depends on watchdog 2 (tables 25 and 26). [0] 1 = p o4/p o2 asser ti on d ep end s on in 1 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 2) . [1] 1 = p o4/p o2 asser ti on d ep end s on in 2 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 3) . [2] 1 = p o4/p o2 asser ti on d ep end s on in 3 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [3] 1 = p o4/p o2 asser ti on d ep end s on in 4 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [4] 1 = po4 (max6872 only) assertion depends on in5 secondary undervoltage/overvoltage threshold (table 4). must be set to 0 for the max6873. [5] 1 = po4 (max6872 only) assertion depends on in6 secondary undervoltage/overvoltage threshold (table 4). must be set to 0 for the max6873. [6] 1 = po4/po2 assertion depends on gpi1 (table 5). 21h 8021h [7] 1 = po4/po2 assertion depends on gpi2 (table 5). [0] 1 = po4/po2 assertion depends on gpi3 (table 5). [1] 1 = po4/po2 assertion depends on gpi4 (table 5). [2] 1 = p o4 ( m ax 6872 onl y) asser ti on d ep end s on p o1 ( tab l e 8) . m ust b e set to 0 for the m ax 6873. [3] 1 = p o4 ( m ax 6872 onl y) asser ti on d ep end s on p o2 ( tab l e 9) . m ust b e set to 0 for the m ax 6873. [4] 1 = po4/po2 assertion depends on po3 (max6872)/po1 (max6873) (tables 10 and 11). [5] 1 = po4/po2 assertion depends on po5 (max6872)/po3 (max6873) (tables 14 and 15). [6] 1 = po4/po2 assertion depends on po6 (max6872)/po4 (max6873) (tables 16 and 17). 22h 8022h [7] 1 = po4/po2 assertion depends on po7 (max6872)/po5 (max6873) (table 18). 23h 8023h [1] 1 = p o4 ( m ax 6872 onl y) asser ti on d ep end s on p o8 ( tab l e 19) . m ust b e set to 0 for the m ax 6873. 40h 8040h [3] 1 = po4/po2 asserts when mr = low (table 6).
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors 24 ______________________________________________________________________________________ table 14. po5 (max6872)/po3 (max6873) output dependency (product 1) register address eeprom memory address bit output assertion conditions [0] 1 = po5/po3 assertion depends on in1 primary undervoltage threshold (table 2). [1] 1 = po5/po3 assertion depends on in2 primary undervoltage threshold (table 3). [2] 1 = po5/po3 assertion depends on in3 primary undervoltage threshold (table 4). [3] 1 = po5/po3 assertion depends on in4 primary undervoltage threshold (table 4). [4] 1 = po5 (max6872 only) assertion depends on in5 primary undervoltage threshold (table 4). must be set to 0 for the max6873. [5] 1 = po5 (max6872 only) assertion depends on in6 primary undervoltage threshold (table 4). must be set to 0 for the max6873. [6] 1 = po5/po3 assertion depends on watchdog 1 (tables 25 and 26). 24h 8024h [7] 1 = po5/po3 assertion depends on watchdog 2 (tables 25 and 26). [0] 1 = p o5/p o3 asser ti on d ep end s on in 1 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 2) . [1] 1 = p o5/p o3 asser ti on d ep end s on in 2 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 3) . [2] 1 = p o5/p o3 asser ti on d ep end s on in 3 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [3] 1 = p o5/p o3 asser ti on d ep end s on in 4 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [4] 1 = po5 (max6872 only) assertion depends on in5 secondary undervoltage/overvoltage threshold (table 4). must be set to 0 for the max6873. [5] 1 = po5 (max6872 only) assertion depends on in6 secondary undervoltage/overvoltage threshold (table 4). must be set to 0 for the max6873. [6] 1 = po5/po3 assertion depends on gpi1 (table 5). 25h 8025h [7] 1 = po5/po3 assertion depends on gpi2 (table 5). [0] 1 = po5/po3 assertion depends on gpi3 (table 5). [1] 1 = po5/po3 assertion depends on gpi4 (table 5). [2] 1 = p o5 ( m ax 6872 onl y) asser ti on d ep end s on p o1 ( tab l e 8) . m ust b e set to 0 for the m ax 6873. [3] 1 = p o5 ( m ax 6872 onl y) asser ti on d ep end s on p o2 ( tab l e 9) . m ust b e set to 0 for the m ax 6873. [4] 1 = po5/po3 assertion depends on po3 (max6872)/po1 (max6873) (tables 10 and 11). [5] 1 = po5/po3 assertion depends on po4 (max6872)/po2 (max6873) (tables 12 and 13). [6] 1 = po5/po3 assertion depends on po6 (max6872)/po4 (max6873) (tables 16 and 17). 26h 8026h [7] 1 = po5/po3 assertion depends on po7 (max6872)/po5 (max6873) (table 18). 2ah 802ah [0] 1 = p o5 ( m ax 6872 onl y) asser ti on d ep end s on p o8 ( tab l e 19) . m ust b e set to 0 for the m ax 6873. 40h 8040h [4] 1 = po5/po3 asserts when mr = low (table 6). t able 14 only applies to po5 of the max6872 and po3 of the max6873. write a 0 to a bit to make the po5/po3 output independent of the respective signal (in_ primary or secondary thresholds, wd1 or wd2, gpi1?pi4, mr , or other programmable outputs). see table 15 for product 2. po5 (max6872)/po3 (max6873) deasserts when product 1 or product 2 = 1.
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 25 t able 15 only applies to po5 of the max6872 and po3 of the max6873. write a 0 to a bit to make the po5/po3 output independent of the respective signal (in_ primary or secondary thresholds, wd1 or wd2, gpi1?pi4, mr , or other programmable outputs). see table 14 for product 1. po5 (max6872)/po3 (max6873) deasserts when product 1 or product 2 = 1. table 15. po5 (max6872)/po3 (max6873) output dependency (product 2) register address eeprom memory address bit output assertion conditions [0] 1 = po5/po3 assertion depends on in1 primary undervoltage threshold (table 2). [1] 1 = po5/po3 assertion depends on in2 primary undervoltage threshold (table 3). [2] 1 = po5/po3 assertion depends on in3 primary undervoltage threshold (table 4). [3] 1 = po5/po3 assertion depends on in4 primary undervoltage threshold (table 4). [4] 1 = po5 (max6872 only) assertion depends on in5 primary undervoltage threshold (table 4). must be set to 0 for the max6873. [5] 1 = po5 (max6872 only) assertion depends on in6 primary undervoltage threshold (table 4). must be set to 0 for the max6873. [6] 1 = po5/po3 assertion depends on watchdog 1 (tables 25 and 26). 27h 8027h [7] 1 = po5/po3 assertion depends on watchdog 2 (tables 25 and 26). [0] 1 = p o5/p o3 asser ti on d ep end s on in 1 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 2) . [1] 1 = p o5/p o3 asser ti on d ep end s on in 2 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 3) . [2] 1 = p o5/p o3 asser ti on d ep end s on in 3 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [3] 1 = p o5/p o3 asser ti on d ep end s on in 4 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [4] 1 = po5 (max6872 only) assertion depends on in5 secondary undervoltage/overvoltage threshold (table 4). must be set to 0 for the max6873. [5] 1 = po5 (max6872 only) assertion depends on in6 secondary undervoltage/overvoltage threshold (table 4). must be set to 0 for the max6873. [6] 1 = po5/po3 assertion depends on gpi1 (table 5). 28h 8028h [7] 1 = po5/po3 assertion depends on gpi2 (table 5). [0] 1 = po5/po3 assertion depends on gpi3 (table 5). [1] 1 = po5/po3 assertion depends on gpi4 (table 5). [2] 1 = p o5 ( m ax 6872 onl y) asser ti on d ep end s on p o1 ( tab l e 8) . m ust b e set to 0 for the m ax 6873. [3] 1 = p o5 ( m ax 6872 onl y) asser ti on d ep end s on p o2 ( tab l e 9) . m ust b e set to 0 for the m ax 6873. [4] 1 = po5/po3 assertion depends on po3 (max6872)/po1 (max6873) (tables 10 and 11). [5] 1 = po5/po3 assertion depends on po4 (max6872)/po2 (max6873) (tables 12 and 13). [6] 1 = po5/po3 assertion depends on po6 (max6872)/po4 (max6873) (tables 16 and 17). 29h 8029h [7] 1 = po5/po3 assertion depends on po7 (max6872)/po5 (max6873) (table 18). 3bh 803bh [4] 1 = p o5 ( m ax 6872 onl y) asser ti on d ep end s on p o8 ( tab l e 19) . m ust b e set to 0 for the m ax 6873. 40h 8040h [4] 1 = po5/po3 asserts when mr = low (table 6).
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors 26 ______________________________________________________________________________________ table 16. po6 (max6872)/po4 (max6873) output dependency (product 1) register address eeprom memory address bit output assertion conditions [0] 1 = po6/po4 assertion depends on in1 primary undervoltage threshold (table 2). [1] 1 = po6/po4 assertion depends on in2 primary undervoltage threshold (table 3). [2] 1 = po6/po4 assertion depends on in3 primary undervoltage threshold (table 4). [3] 1 = po6/po4 assertion depends on in4 primary undervoltage threshold (table 4). [4] 1 = po6 (max6872 only) assertion depends on in5 primary undervoltage threshold (table 4). must be set to 0 for the max6873. [5] 1 = po6 (max6872 only) assertion depends on in6 primary undervoltage threshold (table 4). must be set to 0 for the max6873. [6] 1 = po6/po4 assertion depends on watchdog 1 (tables 25 and 26). 2bh 802bh [7] 1 = po6/po4 assertion depends on watchdog 2 (tables 25 and 26). [0] 1 = p o6/p o4 asser ti on d ep end s on in 1 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 2) . [1] 1 = p o6/p o4 asser ti on d ep end s on in 2 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 3) . [2] 1 = p o6/p o4 asser ti on d ep end s on in 3 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [3] 1 = p o6/p o4 asser ti on d ep end s on in 4 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [4] 1 = po6 (max6872 only) assertion depends on in5 secondary undervoltage/overvoltage threshold (table 4). must be set to 0 for the max6873. [5] 1 = po6 (max6872 only) assertion depends on in6 secondary undervoltage/overvoltage threshold (table 4). must be set to 0 for the max6873. [6] 1 = po6/po4 assertion depends on gpi1 (table 5). 2ch 802ch [7] 1 = po6/po4 assertion depends on gpi2 (table 5). [0] 1 = po6/po4 assertion depends on gpi3 (table 5). [1] 1 = po6/po4 assertion depends on gpi4 (table 5). [2] 1 = p o6 ( m ax 6872 onl y) asser ti on d ep end s on p o1 ( tab l e 8) . m ust b e set to 0 for the m ax 6873. [3] 1 = p o6 ( m ax 6872 onl y) asser ti on d ep end s on p o2 ( tab l e 9) . m ust b e set to 0 for the m ax 6873. [4] 1 = po6/po4 assertion depends on po3 (max6872)/po1 (max6873) (tables 10 and 11). [5] 1 = po6/po4 assertion depends on po4 (max6872)/po2 (max6873) (tables 12 and 13). [6] 1 = po6/po4 assertion depends on po5 (max6872)/po3 (max6873) (tables 14 and 15). 2dh 802dh [7] 1 = po6/po4 assertion depends on po7 (max6872)/po5 (max6873) (table 18). 31h 8031h [0] 1 = p o6 ( m ax 6872 onl y) asser ti on d ep end s on p o8 ( tab l e 19) . m ust b e set to 0 for the m ax 6873. 40h 8040h [5] 1 = po6/po4 asserts when mr = low (table 6). t able 16 only applies to po6 of the max6872 and po4 of the max6873. write a 0 to a bit to make the po6/po4 output independent of the respective signal (in_ primary or secondary thresholds, wd1 or wd2, gpi1?pi4, mr , or other programmable outputs). see table 17 for product 2. po6 (max6872)/po4 (max6873) deasserts when product 1 or product 2 = 1.
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 27 t able 17 only applies to po6 of the max6872 and po4 of the max6873. write a 0 to a bit to make the po6/po4 output independent of the respective signal (in_ primary or secondary thresholds, wd1 or wd2, gpi1?pi4, mr , or other programmable outputs). see table 16 for product 1. po6 (max6872)/po4 (max6873) deasserts when product 1 or product 2 = 1. table 17. po6 (max6872)/po4 (max6873) output dependency (product 2) register address eeprom memory address bit output assertion conditions [0] 1 = po6/po4 assertion depends on in1 primary undervoltage threshold (table 2). [1] 1 = po6/po4 assertion depends on in2 primary undervoltage threshold (table 3). [2] 1 = po6/po4 assertion depends on in3 primary undervoltage threshold (table 4). [3] 1 = po6/po4 assertion depends on in4 primary undervoltage threshold (table 4). [4] 1 = po6 (max6872 only) assertion depends on in5 primary undervoltage threshold (table 4). must be set to 0 for the max6873. [5] 1 = po6 (max6872 only) assertion depends on in6 primary undervoltage threshold (table 4). must be set to 0 for the max6873. [6] 1 = po6/po4 assertion depends on watchdog 1 (tables 25 and 26). 2eh 802eh [7] 1 = po6/po4 assertion depends on watchdog 2 (tables 25 and 26). [0] 1 = p o6/p o4 asser ti on d ep end s on in 1 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 2) . [1] 1 = p o6/p o4 asser ti on d ep end s on in 2 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 3) . [2] 1 = p o6/p o4 asser ti on d ep end s on in 3 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [3] 1 = p o6/p o4 asser ti on d ep end s on in 4 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [4] 1 = po6 (max6872 only) assertion depends on in5 secondary undervoltage/overvoltage threshold (table 4). must be set to 0 for the max6873. [5] 1 = po6 (max6872 only) assertion depends on in6 secondary undervoltage/overvoltage threshold (table 4). must be set to 0 for the max6873. [6] 1 = po6/po4 assertion depends on gpi1 (table 5). 2fh 802fh [7] 1 = po6/po4 assertion depends on gpi2 (table 5). [0] 1 = po6/po4 assertion depends on gpi3 (table 5). [1] 1 = po6/po4 assertion depends on gpi4 (table 5). [2] 1 = p o6 ( m ax 6872 onl y) asser ti on d ep end s on p o1 ( tab l e 8) . m ust b e set to 0 for the m ax 6873. [3] 1 = p o6 ( m ax 6872 onl y) asser ti on d ep end s on p o2 ( tab l e 9) . m ust b e set to 0 for the m ax 6873. [4] 1 = po6/po4 assertion depends on po3 (max6872)/po1 (max6873) (tables 10 and 11). [5] 1 = po6/po4 assertion depends on po4 (max6872)/po2 (max6873) (tables 12 and 13). [6] 1 = po6/po4 assertion depends on po5 (max6872)/po3 (max6873) (tables 14 and 15). 30h 8030h [7] 1 = po6/po4 assertion depends on po7 (max6872)/po5 (max6873) (table 18). 3bh 803bh [5] 1 = p o6 ( m ax 6872 onl y) asser ti on d ep end s on p o8 ( tab l e 19) . m ust b e set to 0 for the m ax 6873. 40h 8040h [5] 1 = po6/po4 asserts when mr = low (table 6).
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors 28 ______________________________________________________________________________________ table 18. po7 (max6872)/po5 (max6873) output dependency register address eeprom memory address bit output assertion conditions [0] 1 = po7/po5 assertion depends on in1 primary undervoltage threshold (table 2). [1] 1 = po7/po5 assertion depends on in2 primary undervoltage threshold (table 3). [2] 1 = po7/po5 assertion depends on in3 primary undervoltage threshold (table 4). [3] 1 = po7/po5 assertion depends on in4 primary undervoltage threshold (table 4). [4] 1 = po7 (max6872 only) assertion depends on in5 primary undervoltage threshold (table 4). must be set to 0 for the max6873. [5] 1 = po7 (max6872 only) assertion depends on in6 primary undervoltage threshold (table 4). must be set to 0 for the max6873. [6] 1 = po7/po5 assertion depends on watchdog 1 (tables 25 and 26). 32h 8032h [7] 1 = po7/po5 assertion depends on watchdog 2 (tables 25 and 26). [0] 1 = p o7/p o5 asser ti on d ep end s on in 1 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 2) . [1] 1 = p o7/p o5 asser ti on d ep end s on in 2 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 3) . [2] 1 = p o7/p o5 asser ti on d ep end s on in 3 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [3] 1 = p o7/p o5 asser ti on d ep end s on in 4 second ar y und er vol tag e/over vol tag e thr eshol d ( tab l e 4) . [4] 1 = po7 (max6872 only) assertion depends on in5 secondary undervoltage/overvoltage threshold (table 4). must be set to 0 for the max6873. [5] 1 = po7 (max6872 only) assertion depends on in6 secondary undervoltage/overvoltage threshold (table 4). must be set to 0 for the max6873. [6] 1 = po7/po5 assertion depends on gpi1 (table 5). 33h 8033h [7] 1 = po7/po5 assertion depends on gpi2 (table 5). [0] 1 = po7/po5 assertion depends on gpi3 (table 5). [1] 1 = po7/po5 assertion depends on gpi4 (table 5). [2] 1 = p o7 ( m ax 6872 onl y) asser ti on d ep end s on p o1 ( tab l e 8) . m ust b e set to 0 for the m ax 6873. [3] 1 = p o7 ( m ax 6872 onl y) asser ti on d ep end s on p o2 ( tab l e 9) . m ust b e set to 0 for the m ax 6873. [4] 1 = po7/po5 assertion depends on po3 (max6872)/po1 (max6873) (tables 10 and 11). [5] 1 = po7/po5 assertion depends on po4 (max6872)/po2 (max6873) (tables 12 and 13). [6] 1 = po7/po5 assertion depends on po5 (max6872)/po3 (max6873) (tables 14 and 15). 34h 8034h [7] 1 = po7/po5 assertion depends on po6 (max6872)/po4 (max6873) (tables 16 and 17). 35h 8035h [0] 1 = p o7 ( m ax 6872 onl y) asser ti on d ep end s on p o8 ( tab l e 19) . m ust b e set to 0 for the m ax 6873. 40h 8040h [6] 1 = po7 asserts when mr = low (table 6). t able 18 only applies to po7 of the max6872 and po5 of the max6873. write a 0 to a bit to make the po7/po5 output independent of the respective signal (in_ primary or secondary thresholds, wd1 or wd2, gpi1?pi4, mr , or other programmable outputs).
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 29 t able 19 only applies to po8 of the max6872. write a 0 to a bit to make the po8 output independent of the respective signal (in1?n6 primary or secondary thresholds, wd1 or wd2, gpi1?pi4, mr , or other pro- grammable outputs). output stage configurations independently program each programmable output as active high or active low ( table 20). additionally, pro- gram each programmable output as weak pullup, push- pull, open-drain, or charge pump (tables 21 and 22). every programmable output can be configured as open-drain or weak pullup; however, only po1?o4 (max6872) or po1?o2 (max6873) can be configured as charge-pump outputs, and only po5?o8 (max6872) or po3?o5 (max6873) can be configured as push-pull outputs. finally, set the po_ timeout period for each programmable output ( table 23). an internal 10k ? resistor provides the pullup resistance for outputs configured as weak pullup stages. program each weak pullup output stage to refer to abp or one of the in3?n6 inputs. the programmable outputs source up to 10ma and sink up to 4ma when configured as push- pull stages. program each push-pull output stage to ref- erence to one of in3?n6. po1?o4 (max6872)/ po1po2 (max6873) pull to v abp + 5v when configured as charge-pump outputs. table 19. po8 (max6872 only) output dependency register address eeprom memory address bit output assertion conditions [0] 1 = po8 assertion depends on in1 primary undervoltage threshold (table 2). [1] 1 = po8 assertion depends on in2 primary undervoltage threshold (table 3). [2] 1 = po8 assertion depends on in3 primary undervoltage threshold (table 4). [3] 1 = po8 assertion depends on in4 primary undervoltage threshold (table 4). [4] 1 = po8 assertion depends on in5 primary undervoltage threshold (table 4). [5] 1 = po8 assertion depends on in6 primary undervoltage threshold (table 4). [6] 1 = po8 assertion depends on watchdog 1 (tables 25 and 26). 36h 8036h [7] 1 = po8 assertion depends on watchdog 2 (tables 25 and 26). [0] 1 = po8 assertion depends on in1 secondary undervoltage/overvoltage threshold (table 2). [1] 1 = po8 assertion depends on in2 secondary undervoltage/overvoltage threshold (table 3). [2] 1 = po8 assertion depends on in3 secondary undervoltage/overvoltage threshold (table 4). [3] 1 = po8 assertion depends on in4 secondary undervoltage/overvoltage threshold (table 4). [4] 1 = po8 assertion depends on in5 secondary undervoltage/overvoltage threshold (table 4). [5] 1 = po8 assertion depends on in6 secondary undervoltage/overvoltage threshold (table 4). [6] 1 = po8 assertion depends on gpi1 (table 5). 37h 8037h [7] 1 = po8 assertion depends on gpi2 (table 5). [0] 1 = po8 assertion depends on gpi3 (table 5). [1] 1 = po8 assertion depends on gpi4 (table 5). [2] 1 = po8 assertion depends on po1 (table 8). [3] 1 = po8 assertion depends on po2 (table 9). [4] 1 = po8 assertion depends on po3 (tables 10 and 11). [5] 1 = po8 assertion depends on po4 (tables 12 and 13). [6] 1 = po8 assertion depends on po5 (tables 14 and 15). 38h 8038h [7] 1 = po8 assertion depends on po6 (tables 16 and 17). 39h 8039h [0] 1 = po8 assertion depends on po7 (table 18). 40h 8040h [7] 1 = po8 asserts when mr = low (table 6).
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors 30 ______________________________________________________________________________________ table 20. programmable output active states register address eeprom memory address bit range description [0] po1 (max6872 only). 0 = active low, 1 = active high. [1] po2 (max6872 only). 0 = active low, 1 = active high. [2] po3 (max6872)/po1 (max6873). 0 = active low, 1 = active high. [3] po4 (max6872)/po2 (max6873). 0 = active low, 1 = active high. [4] po5 (max6872)/po3 (max6873). 0 = active low, 1 = active high. [5] po6 (max6872)/po4 (max6873). 0 = active low, 1 = active high. [6] po7 (max6872)/po5 (max6873). 0 = active low, 1 = active high. 3ah 803ah [7] po8 (max6872 only). 0 = active low, 1 = active high. register address eeprom memory address bit range affected output description 11h 8011h [6:4] po1 15h 8015h [6:4] po2 1ch 801ch [7:5] po3 23h 8023h [7:5] po4 000 = open drain, 001 = weak pullup to in3, 010 = weak pullup to in4, 011 = weak pullup to in5, 100 = weak pullup to in6, 101 = weak pullup to abp, 110 = charge-pump output, 111 = not used. 2ah 802ah [7:4] po5 31h 8031h [7:4] po6 35h 8035h [7:4] po7 39h 8039h [7:4] po8 0000 = open drain, 0001 = weak pullup to in3, 0010 = weak pullup to in4, 0011 = weak pullup to in5, 0100 = weak pullup to in6, 0101 = weak pullup to abp, 0110 = push-pull to in3, 0111 = push-pull to in4, 1000 = push-pull to in5, 1001 = push-pull to in6, 1010?111 = not used. table 21. programmable output stage options (max6872) table 22. programmable output stage options (max6873) register address eeprom memory address bit range affected output description 1ch 801ch [7:5] po1 23h 8023h [7:5] po2 000 = open drain, 001 = weak pullup to in3, 010 = weak pullup to in4, 011?00 = not used, 101 = weak pullup to abp, 110 = charge-pump output, 111 = not used. 2ah 802ah [7:4] po3 31h 8031h [7:4] po4 35h 8035h [7:4] po5 0000 = open drain, 0001 = weak pullup to in3, 0010 = weak pullup to in4, 0011?100 = not used, 0101 = weak pullup to abp, 0110 = push-pull to in3, 0111 = push-pull to in4, 1000?111 = not used.
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 31 charge-pump output configuration configure the programmable outputs of the max6872/ max6873 as charge-pump outputs to drive n-channel fets for power-supply sequencing applications. only po1?o4 (max6872) or po1 and po2 (max6873) can be configured as charge-pump output stages. the charge-pump output high voltage is typically v abp +5.5v when unloaded. push-pull output configuration the max6872/max6873s?programmable outputs sink 4ma and source 10ma when configured as push-pull outputs. only po5?o8 (max6872) or po3?o5 (max6873) can be configured as push-pull output stages. the push-pull output stages refer to any of in3?n6 (max6872)/in3?n4 (max6873) as configured in tables 21 and 22. use the push-pull output configu- ration to drive loads with fast rise/fall times, or those with low impedance. weak pullup output configuration the max6872/max6873s?programmable outputs sink 4ma when configured as weak pullups. the weak pullup of 10k ? refers to any of in3?n6 (max6872)/ in3?n4 (max6873) or abp as configured in tables 21 and 22. all programmable outputs of the max6872/max6873 may be configured as weak pullups. open-drain output configuration connect an external pullup resistor from the program- mable output to an external voltage when configured as an open-drain output. po1?o4 (po1 and po2 for the max6873) may be pulled up to +13.2v. po5?o8 (po3?o5 for the max6873) may be pulled up to a voltage less than or equal to abp. choose the pullup resistor depending on the number of devices connect- ed to the open-drain output and the allowable current consumption. the open-drain output configuration allows wire-ored connections, and provides flexibility in setting the pullup current. configuring the max6872/max6873 the max6872/max6873 factory-default configuration sets all eeprom registers to 00h except register 3ah, which is set to ffh. this configuration sets all of the pro- grammable outputs as active high, open drain (putting all outputs into high-impedance states until the device is reconfigured by the user). each device requires configu- ration before full power is applied to the system. to con- figure the max6872/max6873, first apply an input voltage to in1 or one of in3?n6 (max6872)/in3?n4 (max6873) (see the powering the max6872/max6873 section). v in1 > +4v or one of v in3 ? in6 > +2.7v, to ensure device operation. next, transmit data through the serial interface. use the block write protocol to quickly configure the device. write to the configuration registers first to ensure the device is configured properly. after completing the setup procedure, use the read word pro- tocol to verify the data from the configuration registers. lastly, use the write word protocol to write this data to the eeprom registers. after completing eeprom regis- ter configuration, apply full power to the system to begin normal operation. the non-volatile eeprom stores the latest configuration upon removal of power. write zeros to all eeprom registers to clear the memory. software reboot a software reboot allows the user to restore the eeprom configuration to the volatile registers without cycling the power supplies. use the send byte com- mand with data byte 88h to initiate a software reboot. the 3.5ms (max) power-up delay also applies after a software reboot. table 23. po_ timeout periods affected outputs register address eeprom memory address bit range max6872 max6873 description 11h 8011h [3:1] po1 15h 8015h [3:1] po2 1ch 801ch [4:2] po3 po1 23h 8023h [4:2] po4 po2 2ah 802ah [3:1] po5 po3 31h 8031h [3:1] po6 po4 35h 8035h [3:1] po7 po5 39h 8039h [3:1] po8 000 = 25? 001 = 1.5625ms 010 = 6.25ms 011 = 25ms 100 = 50ms 101 = 200ms 110 = 400ms 111 = 1600ms
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors 32 ______________________________________________________________________________________ stop condition repeated start condition start condition t high t low t r t f t su:dat t su:sta t su:sto t hd:sta t buf t hd:sta t hd:dat scl sda start condition figure 2. serial-interface timing details data line stable, data valid sda scl change of data allowed figure 3. bit transfer p s start condition sda scl stop condition figure 4. start and stop conditions smbus/i 2 c-compatible serial interface the max6872/max6873 feature an i 2 c/smbus-compati- ble serial interface consisting of a serial data line (sda) and a serial clock line (scl). sda and scl allow bidirec- tional communication between the max6872/max6873 and the master device at clock rates up to 400khz. figure 2 shows the interface timing diagram. the max6872/max6873 are transmit/receive slave-only devices, relying upon a master device to generate a clock signal. the master device (typically a microcon- troller) initiates data transfer on the bus and generates scl to permit that transfer. a master device communicates to the max6872/ max6873 by transmitting the proper address followed by command and/or data words. each transmit sequence is framed by a start (s) or repeated start (sr) condi- tion and a stop (p) condition. each word transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse. scl is a logic input, while sda is a logic input/open- drain output. scl and sda both require external pullup resistors to generate the logic-high voltage. use 4.7k ? for most applications. bit transfer each clock pulse transfers one data bit. the data on sda must remain stable while scl is high ( figure 3), otherwise the max6872/max6873 register a start or stop condition ( figure 4) from the master. sda and scl idle high when the bus is not busy.
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 33 start and stop conditions both scl and sda idle high when the bus is not busy. a master device signals the beginning of a transmission with a start (s) condition ( figure 4) by transitioning sda from high to low while scl is high. the master device issues a stop (p) condition ( figure 4) by transi- tioning sda from low to high while scl is high. a stop condition frees the bus for another transmission. the bus remains active if a repeated start condition is gener- ated, such as in the block read protocol (see figure 7). early stop conditions the max6872/max6873 recognize a stop condition at any point during transmission except if a stop condition occurs in the same high pulse as a start condition. this condition is not a legal i 2 c format. at least one clock pulse must separate any start and stop conditions. repeated start conditions a repeated start (sr) condition may indicate a change of data direction on the bus. such a change occurs when a command word is required to initiate a read operation (see figure 7). sr may also be used when the bus master is writing to several i 2 c devices and does not want to relinquish control of the bus. the max6872/max6873 serial interface supports continu- ous write operations with or without an sr condition separating them. continuous read operations require sr conditions because of the change in direction of data flow. acknowledge the acknowledge bit (ack) is the 9th bit attached to any 8-bit data word. the receiving device always generates an ack. the max6872/max6873 generate an ack when receiving an address or data by pulling sda low during the 9th clock period ( figure 5). when transmitting data, such as when the master device reads data back from the max6872/max6873, the max6872/max6873 wait for the master device to generate an ack. monitoring ack allows for detection of unsuccessful data transfers. an unsuccessful data transfer occurs if the receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. the max6872/max6873 generate a nack after the slave address during a software reboot, while writing to the eeprom, or when receiving an illegal memory address. slave address the max6872/max6873 slave address conforms to the following table : scl 1 s 2 89 sda by transmitter sda by receiver start condition clock pulse for acknowledge figure 5. acknowledge x = don? care. sa7 (msb) sa6 sa5 sa4 sa3 sa2 sa1 sa0 (lsb) 1 010 a1 a0 x r/ w
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors 34 ______________________________________________________________________________________ sa7 through sa4 represent the standard interface address (1010) for devices with eeprom. sa3 and sa2 correspond to the a1 and a0 address inputs of the max6872/max6873 (hard-wired as logic-low or logic- high). sa0 is a read/write flag bit (0 = write, 1 = read). the a0 and a1 address inputs allow up to four max6872/max6873 devices to connect to one bus. connect a0 and a1 to gnd or to the serial interface power supply (see figure 6). send byte the send byte protocol allows the master device to send one byte of data to the slave device (see figure 7). the send byte presets a register pointer address for a sub- sequent read or write. the slave sends a nack instead of an ack if the master tries to send an address that is not allowed. if the master sends 80h, 81h, or 82h, the data is ack. this could be start of the write byte/word protocol, and the slave expects at least one further data byte. if the master sends a stop condition, the internal address pointer does not change. if the master sends 84h, this signifies that the block read protocol is expected, and a repeated start condition should follow. the device reboots if the master sends 88h. the send byte procedure follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends an 8-bit data byte. 5) the addressed slave asserts an ack on sda. 6) the master sends a stop condition. write byte/word the write byte/word protocol allows the master device to write a single byte in the register bank, preset an eeprom (configuration or user) address for a subse- quent read, or to write a single byte to the configuration or user eeprom (see figure 7). the write byte/word procedure follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends an 8-bit command code. 5) the addressed slave asserts an ack on sda. 6) the master sends an 8-bit data byte. 7) the addressed slave asserts an ack on sda. 8) the master sends a stop condition or sends another 8-bit data byte. 9) the addressed slave asserts an ack on sda. 10) the master sends a stop condition. to write a single byte to the register bank, only the 8-bit command code and a single 8-bit data byte are sent. the command code must be in the range of 00h to 45h. the data byte is written to the register bank if the com- mand code is valid. the slave generates a nack at step 5 if the command code is invalid. to preset an eeprom (configuration or user) address for a subsequent read, the 8-bit command code and a single 8-bit data byte are sent. the command code must be 80h if the write is to be directed into the config- uration eeprom, or 81h or 82h, if the write is to be sda scl 1 msb lsb start 01 0 a1 a0 x r/w ack figure 6. slave address
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 35 write byte format s s address address 7 bits 7 bits send byte format receive byte format wr wr ack ack data data 8 bits 8 bits ack p ack p data byte?resets the internal address pointer. data byte?eads data from the register commanded by the last read byte or write byte transmission. also dependent on a send byte. write word format s address wr ack ack ack ack command data data p 7 bits 8 bits 8 bits 8 bits slave address equivalent to chip- select line of a 3- wire interface. command byte msb of the eeprom register being written. data byte?irst byte is the lsb of the eeprom address. second byte is the actual data. block write format s address wr ack command ack byte count= n ack data byte 1 ack data byte ... ack data byte n ack p 7 bits 83h 8 bits 8 bits 8 bits slave address equivalent to chip- select line of a 3- wire interface. command byte prepares device for block operation. data byte?ata goes into the register set by the command byte. block read format s address wr ack command ack sr address wr ack 8 bits byte count= 16 ack data byte 1 ack data byte ... ack data byte n ack p 7 bits 84h 7 bits 10h 8 bits 8 bits 8 bits slave address equivalent to chip- select line of a 3- wire interface. command byte prepares device for block operation. slave address equivalent to chip- select line of a 3- wire interface. data byte?ata goes into the register set by the command byte. s = start condition. p = stop condition. shaded = slave transmission. sr = repeated start condition. slave address equivalent to chip- select line of a 3- wire interface. slave address equivalent to chip- select line of a 3- wire interface. s address wr ack command ack data ack p 7 bits 8 bits 8 bits slave address equivalent to chip- select line of a 3- wire interface. command byte selects register being written. data byte?ata goes into the register set by the command byte if the command is below 50h. if the command is 80h, 81h, or 82h, the data byte presets the lsb of an eeprom address. 10 0 00 1 0 figure 7. smbus/i 2 c protocols
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors 36 ______________________________________________________________________________________ directed into the user eeprom. if the command code is 80h, the data byte must be in the range of 00h to 45h. if the command code is 81h or 82h, the data byte can be 00h to ffh. a nack is generated in step 7 if none of the above conditions are true. to write a single byte of data to the user or configuration eeprom, the 8-bit command code and a single 8-bit data byte are sent. the following 8-bit data byte is writ- ten to the addressed eeprom location. block write the block write protocol allows the master device to write a block of data (1 to 16 bytes) to the eeprom or to the register bank (see figure 7). the destination address must already be set by the send byte or write byte protocol and the command code must be 83h. if the number of bytes to be written causes the address pointer to exceed 45h for the configuration register or configuration eeprom, the address pointer stays at 45h, overwriting this memory address with the remain- ing bytes of data. the last data byte sent is stored at register address 45h. if the number of bytes to be writ- ten exceeds the address pointer ffh for the user eep- rom, the address pointer loops back to 00h, and continues writing bytes until all data is written. the block write procedure follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends the 8-bit command code for block write (83h). 5) the addressed slave asserts an ack on sda. 6) the master sends the 8-bit byte count (1 to 16 bytes) n. 7) the addressed slave asserts an ack on sda. 8) the master sends 8 bits of data. 9) the addressed slave asserts an ack on sda. 10) repeat steps 8 and 9 one time. 11) the master generates a stop condition. receive byte the receive byte protocol allows the master device to read the register content of the max6872/max6873 (see figure 7). the eeprom or register address must be preset with a send byte or write word protocol first. once the read is complete, the internal pointer increas- es by one. repeating the receive byte protocol reads the contents of the next address. the receive byte pro- cedure follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a read bit (high). 3) the addressed slave asserts an ack on sda. 4) the slave sends 8 data bits. 5) the master asserts a nack on sda. 6) the master generates a stop condition. block read the block read protocol allows the master device to read a block of 16 bytes from the eeprom or register bank (see figure 7). read fewer than 16 bytes of data by issuing an early stop condition from the master, or by generating a nack with the master. the send byte or write byte protocol predetermines the destination address with a command code of 84h. the block read procedure follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends 8 bits of the block read command (84h). 5) the slave asserts an ack on sda, unless busy. 6) the master generates a repeated start condition. 7) the master sends the 7-bit slave address and a read bit (high). 8) the slave asserts an ack on sda. 9) the slave sends the 8-bit byte count (16). 10) the master asserts an ack on sda. 11) the slave sends 8 bits of data. 12) the master asserts an ack on sda. 13) repeat steps 8 and 9 fifteen times. 14) the master generates a stop condition. address pointers use the send byte protocol to set the register address pointers before read and write operations. for the con- figuration registers, valid address pointers range from 00h to 45h. register addresses outside of this range result in a nack being issued from the max6872/ max6873. when using the block write protocol, the address pointer automatically increments after each data byte, except when the address pointer is already at 45h. if the address pointer is already 45h, and more data bytes are being sent, these subsequent bytes overwrite address 45h repeatedly, leaving only the last data byte sent stored at this register address.
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 37 for the configuration eeprom, valid address pointers range from 8000h to 8045h. registers 8046h to 804fh are reserved and should not be overwritten. register addresses from 8050h to 80ffh return a nack from the max6872/max6873. when using the block write protocol, the address pointer automatically increments after each data byte, except when the address pointer is already at 8045h. if the address pointer is already 8045h, and more data bytes are being sent, these sub- sequent bytes overwrite address 8045h repeatedly, leaving only the last data byte sent stored at this regis- ter address. for the user eeprom, valid address pointers range from 8100h to 81ffh and 8200h to 82ffh. block write and block read protocols allow the address pointer to reset (to 8100h or 8200h) when attempting to write or read beyond 81ffh or 82ffh. configuration eeprom the configuration eeprom addresses range from 8000h to 8045h. write data to the configuration eeprom to automatically set up the max6872/max6873 upon power- up. data transfers from the configuration eeprom to the configuration registers when abp exceeds uvlo during power-up or after a software reboot. after abp exceeds uvlo, an internal 1mhz clock starts after a 5? delay, and data transfer begins. data transfer disables access to the configuration registers and eeprom. the data transfer from eeprom to configuration registers takes 3.5ms (max). read configuration eeprom data at any time after power-up or software reboot. write commands to the configuration eeprom are allowed at any time after power-up or software reboot, unless the configura- tion lock bit is set (see table 28). the maximum cycle time to write a single byte is 11ms (max). user eeprom the 512 byte user eeprom addresses range from 8100h to 82ffh (see figure 8). store software-revision data, board-revision data, and other data in these reg- isters. the maximum cycle time to write a single byte is 11ms (max). configuration register bank and eeprom the configuration registers can be directly modified by the serial interface without modifying the eeprom after the power-up procedure terminates and the configura- tion eeprom data has been loaded into the configura- tion register bank. use the write byte or block write protocols to write directly to the configuration registers. changes to the configuration registers take effect immediately and are lost upon power removal. at device power-up, the register bank loads configura- tion data from the eeprom. configuration data may be directly altered in the register bank during application development, allowing maximum flexibility. transfer the new configuration data, byte by byte, to the configura- tion eeprom with the write byte protocol. the next device power-up or software reboot automatically loads the new configuration. configuring the watchdog timers (registers 3ch?fh) a watchdog timer monitors microprocessor (p) soft- ware execution for a stalled condition and resets the ? if it stalls. the output of a watchdog timer (one of the table 24. register map register address eeprom memory address read/ write description 00h 8000h r/w in1 primary undervoltage detector threshold (table 2) 01h 8001h r/w in2 primary undervoltage detector threshold (table 3) 02h 8002h r/w in3 primary undervoltage detector threshold (table 4) 03h 8003h r/w in4 primary undervoltage detector threshold (table 4) 04h 8004h r/w in5 primary undervoltage detector threshold (max6872 only) (table 4) 05h 8005h r/w in6 primary undervoltage detector threshold (max6872 only) (table 4) 06h 8006h r/w in1 secondary undervoltage/overvoltage detector threshold (table 2). 07h 8007h r/w in2 secondary undervoltage/overvoltage detector threshold (table 3) 08h 8008h r/w in3 secondary undervoltage/overvoltage detector threshold (table 4) 09h 8009h r/w in4 secondary undervoltage/overvoltage detector threshold (table 4) 0ah 800ah r/w in5 secondary undervoltage/overvoltage detector threshold (max6872 only) (table 4)
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors 38 ______________________________________________________________________________________ table 24. register map (continued) register address eeprom memory address read/ write description 0bh 800bh r/w in6 secondary undervoltage/overvoltage detector threshold (max6872 only) (table 4) 0ch 800ch r/w secondary undervoltage/overvoltage selection (tables 2, 4) 0dh 800dh r/w threshold range selection (tables 2, 3, 4) 0eh 800eh r/w po1 (max6872 only) input selection (table 8) 0fh 800fh r/w po1 (max6872 only) input selection (table 8) 10h 8010h r/w po1 (max6872 only) input selection (table 8) 11h 8011h r/w po1 (max6872 only) input selection, po_ timeout period, and output type selection (tables 8, 21, and 23) 12h 8012h r/w po2 (max6872 only) input selection (table 9) 13h 8013h r/w po2 (max6872 only) input selection (table 9) 14h 8014h r/w po2 (max6872 only) input selection (table 9) 15h 8015h r/w po2 (max6872 only) input selection, po_ timeout period, and output type selection (tables 9, 21, and 23) 16h 8016h r/w po3 (max6872)/po1 (max6873) input selection?roduct 1 (table 10) 17h 8017h r/w po3 (max6872)/po1 (max6873) input selection?roduct 1 (table 10) 18h 8018h r/w po3 (max6872)/po1 (max6873) input selection?roduct 1 (table 10) 19h 8019h r/w po3 (max6872)/po1 (max6873) input selection?roduct 2 (table 11) 1ah 801ah r/w po3 (max6872)/po1 (max6873) input selection?roduct 2 (table 11) 1bh 801bh r/w po3 (max6872)/po1 (max6873) input selection?roduct 2 (table 11) 1ch 801ch r/w po3 (max6872)/po1 (max6873) input selection?roducts 1 and 2, po_ timeout period, and output type selection (tables 10, 11, 21, 22, and 23) 1dh 801dh r/w po4 (max6872)/po2 (max6873) input selection?roduct 1 (table 12) 1eh 801eh r/w po4 (max6872)/po2 (max6873) input selection?roduct 1 (table 12) 1fh 801fh r/w po4 (max6872)/po2 (max6873) input selection?roduct 1 (table 12) 20h 8020h r/w po4 (max6872)/po2 (max6873) input selection?roduct 2 (table 13) 21h 8021h r/w po4 (max6872)/po2 (max6873) input selection?roduct 2 (table 13) 22h 8022h r/w po4 (max6872)/po2 (max6873) input selection?roduct 2 (table 13) 23h 8023h r/w po4 (max6872)/po2 (max6873) input selection?roducts 1 and 2, po_ timeout period, and output type selection (tables 12, 13, 21, 22, and 23) 24h 8024h r/w po5 (max6872)/po3 (max6873) input selection?roduct 1 (table 14) 25h 8025h r/w po5 (max6872)/po3 (max6873) input selection?roduct 1 (table 14) 26h 8026h r/w po5 (max6872)/po3 (max6873) input selection?roduct 1 (table 14) 27h 8027h r/w po5 (max6872)/po3 (max6873) input selection?roduct 2 (table 15) 28h 8028h r/w po5 (max6872)/po3 (max6873) input selection?roduct 2 (table 15) 29h 8029h r/w po5 (max6872)/po3 (max6873) input selection?roduct 2 (table 15) 2ah 802ah r/w po5 (max6872)/po3 (max6873) input selection?roducts 1 and 2, po_ timeout period, and output type selection (tables 14, 21, 22, and 23) 2bh 802bh r/w po6 (max6872)/po4 (max6873) input selection?roduct 1 (table 16) 2ch 802ch r/w po6 (max6872)/po4 (max6873) input selection?roduct 1 (table 16)
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 39 table 24. register map (continued) register address eeprom memory address read/ write description 2dh 802dh r/w po6 (max6872)/po4 (max6873) input selection?roduct 1 (table 16) 2eh 802eh r/w po6 (max6872)/po4 (max6873) input selection?roduct 2 (table 17) 2fh 802fh r/w po6 (max6872)/po4 (max6873) input selection?roduct 2 (table 17) 30h 8030h r/w po6 (max6872)/po4 (max6873) input selection?roduct 2 (table 17) 31h 8031h r/w po6 (max6872)/po4 (max6873) input selection?roducts 1 and 2, po_ timeout period, and output type selection (tables 16, 21, 22, and 23) 32h 8032h r/w po7 (max6872)/po5 (max6873) input selection (table 18) 33h 8033h r/w po7 (max6872)/po5 (max6873) input selection (table 18) 34h 8034h r/w po7 (max6872)/po5 (max6873) input selection (table 18) 35h 8035h r/w po7 (max6872)/po5 (max6873) input selection, po_ timeout period, and output type selection (tables 18, 21, 22, and 23) 36h 8036h r/w po8 (max6872 only) input selection (table 19) 37h 8037h r/w po8 (max6872 only) input selection (table 19) 38h 8038h r/w po8 (max6872 only) input selection (table 19) 39h 8039h r/w po8 (max6872 only) input selection, po_ timeout period, and output type selection (tables 19, 21, 22, and 23) 3ah 803ah r/w programmable output polarity (active high/active low) (table 20) 3bh 803bh r/w gpi_ input polarity, po5, po6 (tables 5, 15, and 17) 3ch 803ch r/w wd1 input selection and timeout enable (table 25) 3dh 803dh r/w wd1 initial and normal timeout duration (table 26) 3eh 803eh r/w wd2 input selection and timeout enable (table 25) 3fh 803fh r/w wd2 initial and normal timeout duration (table 26) 40h 8040h r/w mr input and programmable output behavior (table 6) 41h 8041h r/w margin and programmable output behavior (table 7) 42h 8042h r/w programmable output state with margin assertion (table 7) 43h 8043h r/w user eeprom write disable (table 29) 44h 8044h r/w set to 0 45h 8045h r/w configuration lock (table 28) 46h 8046h reserved. should not be overwritten. 47h 8047h reserved. should not be overwritten. 48h 8048h reserved. should not be overwritten. 49h 8049h reserved. should not be overwritten. 4ah 804ah reserved. should not be overwritten. 4bh 804bh reserved. should not be overwritten. 4ch 804ch reserved. should not be overwritten. 4dh 804dh reserved. should not be overwritten. 4eh 804eh reserved. should not be overwritten. 4fh 804fh reserved. should not be overwritten.
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors 40 ______________________________________________________________________________________ table 24. register map (continued) register address eeprom memory address read/ write description 50h r reserved. should not be overwritten. 51h r reserved. should not be overwritten. 52h r reserved. should not be overwritten. 53h r reserved. should not be overwritten. 54h r reserved. should not be overwritten. 55h r reserved. should not be overwritten. 56h r reserved. should not be overwritten. 57h r reserved. should not be overwritten. 58h r reserved. should not be overwritten. 59h r reserved. should not be overwritten. 5ah r reserved. should not be overwritten. 5bh r reserved. should not be overwritten. 5ch r reserved. should not be overwritten. 5dh r reserved. should not be overwritten. 5eh r reserved. should not be overwritten. 5fh r reserved. should not be overwritten. 60h r fault flags for in1?n6 (primary thresholds) (table 27) 61h r fault flags for in1?n6 (secondary thresholds) (table 27) 62h r fault flags for wd_, gpi_, and mr (table 27) 8100h user eeprom 81ffh 8000h configuration eeprom 8045h 00h register bank configuration data reserved fault registers (read only) 62h 45h 60h 8200h user eeprom 82ffh figure 8. memory map
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 41 programmable outputs) connects to the reset input or a nonmaskable interrupt of the ?. registers 3ch?fh configure the watchdog functionality of the max6872/max6873. program each watchdog timer to assert one or more programmable outputs (see tables 8?9). program each watchdog timer to reset on one of the gpi_ inputs, one of the programmable out- puts, or a combination of one gpi_ input and one pro- grammable output. each watchdog timer features independent initial and normal watchdog timeout periods. the initial watchdog timeout period applies immediately after power-up, after a reset event takes place, or after enabling the watchdog timer. the initial watchdog timeout period allows the ? to perform its initialization process. if no pulse occurs during the initial watchdog timeout period, the ? is taking too long to initialize, indicating a potential problem. the normal watchdog timeout period applies in every other cycle after the initial watchdog timeout period occurs. the normal watchdog timeout period monitors a pulsed output of the p that indicates when normal processor behavior occurs. if no pulse occurs during the normal watchdog timeout period, this indicates that the processor has stopped operating or is stuck in an infinite execution loop. disable or enable each initial timeout period through reg- isters 3ch and 3eh. registers 3dh and 3fh program the initial and normal watchdog timeout periods, and enable or disable each watchdog timer. see tables 25 and 26 for a summary of the watchdog behavior. fault detector registers 60h?2h store all fault conditions, including undervoltage, overvoltage, gpi_, and watchdog timer faults (see table 27). fault registers are read-only and lose contents upon power removal. the first read com- mand from the fault registers after power-up gives invalid data. any mr assertion writes to the fault register. reading the fault register clears all fault flags. both gpi_ and wd_ bits assert if any of the gpi_ inputs are config- ured as watchdog inputs (wd_) and a watchdog fault occurs. table 25. watchdog inputs (addresses 3ch (watchdog 1), 3eh (watchdog 2)) register address eeprom memory address bit range description [1:0] watchdog input selection: 00 = gpi1 01 = gpi2 10 = gpi3 11 = gpi4 [4:2] watchdog internal input selection: 000 = po1 (max6872), not used (max6873) 001 = po2 (max6872), not used (max6873) 010 = po3 (max6872), po1 (max6873) 011 = po4 (max6872), po2 (max6873) 100 = po5 (max6872), po3 (max6873) 101 = po6 (max6872), po4 (max6873) 110 = po7 (max6872), po5 (max6873) 111 = po8 (max6872), not used (max6873) [6:5] watchdog dependency on inputs: 00 = 11 = watchdog clear depends on both gpi_ from 3ch[1:0] (watchdog 1) or 3eh[1:0] (watchdog 2) and po_ from 3ch[4:2] (watchdog 1) or 3eh[4:2] (watchdog 2). 01 = watchdog clear depends only on po_ from 3ch[4:2] (watchdog 1) or 3eh[4:2] (watchdog 2). 10 = watchdog clear depends only on gpi_ from 3ch[1:0] (watchdog 1) or 3eh[1:0] (watchdog 2). 3ch (watchdog 1) 3eh (watchdog 2) 803ch (watchdog 1) 803eh (watchdog 2) [7] initial watchdog timeout period enable: 0 = disables initial watchdog timeout period (normal watchdog timeout period not affected). 1 = enables initial watchdog timeout period.
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors 42 ______________________________________________________________________________________ configuration lock lock the configuration register bank and configuration eeprom contents after initial programming by setting the lock bit high (see table 28). locking the configura- tion prevents write operations to all registers except the configuration lock register. clear the lock bit to recon- figure the device. write disable a unique write disable feature protects the max6872/ max6873 from inadvertent user eeprom writes. as input voltages that power the serial interface, a p, or any other writing devices fall, unintentional data may be written onto the data bus. the user eeprom write dis- able function (see table 29) ensures that unintentional data does not corrupt the max6872/max6873 eep- rom data. applications information configuration download at power-up the configuration of the max6872/max6873 (undervolt- age/overvoltage thresholds, po_ timeout periods, watchdog behavior, programmable output conditions and configurations, etc.) depends on the contents of the eeprom. the eeprom comprises buffered latches that store the configuration. the local volatile memory latches lose their contents at power-down. therefore, at power-up, the device configuration must be restored by downloading the contents of the eeprom (non-volatile memory) to the local latches. this download occurs in a number of steps: 1) programmable outputs go high impedance with no power applied to the device. 2) when abp exceeds +1v, all programmable out- puts are weakly pulled to gnd through a 10? current sink. 3) when abp exceeds uvlo, the configuration eep- rom starts to download its contents to the volatile configuration registers. the programmable outputs assume their programmed conditional output state when download is complete. 4) any attempt to communicate with the device prior to this download completion results in a nack being issued from the max6872/max6873. table 26. watchdog timeout period selection (addresses 3dh (watchdog 1), 3fh (watchdog 2)) register address eeprom memory address bit range description [2:0] normal watchdog timeout period: 000 = 6.25ms 001 = 25ms 010 = 100ms 011 = 400ms 100 = 1.6s 101 = 6.4s 110 = 25.6s 111 = 102.4s [5:3] initial watchdog timeout period (immediately following power-up, reset event, or enabling watchdog): 000 = 6.25ms 001 = 25ms 010 = 100ms 011 = 400ms 100 = 1.6s 101 = 6.4s 110 = 25.6s 111 = 102.4s [6] watchdog enable: 0 = disables watchdog timer 1 = enables watchdog timer 3dh (watchdog 1) 3fh (watchdog 2) 803dh (watchdog 1) 803fh (watchdog 2) [7] not used
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 43 forcing programmable outputs high during power-up a weak 10? pulldown holds all programmable outputs low during power-up until abp exceeds the undervolt- age lockout (uvlo) threshold. applications requiring a guaranteed high programmable output for abp down to gnd require external pullup resistors to maintain the logic state until abp exceeds uvlo. use 20k ? resis- tors for most applications. driving high-side mosfet switches with the max6872/max6873 high-side mosfet switches are commonly used in power-supply sequencing applications. first, configure the programmable output of the max6872/max6873 as an active-low charge-pump output and set the condi- tions to assert this output. connect the programmable output to the gate of an n-channel mosfet. as the conditions to deassert this output are met, the output deasserts high (v abp +5v), turning on the fet, thus allowing the voltage on the drain to pass through to the downstream device (see figure 9). table 27. fault registers (60h?2h) register address bit range description [0] 1 = in1 falls below primary undervoltage threshold. [1] 1 = in2 falls below primary undervoltage threshold. [2] 1 = in3 falls below primary undervoltage threshold. [3] 1 = in4 falls below primary undervoltage threshold. [4] 1 = in5 (max6872 only) falls below primary undervoltage threshold. [5] 1 = in6 (max6872 only) falls below primary undervoltage threshold. 60h [7:6] not used. [0] 1 = in1 falls below secondary undervoltage threshold or rises above secondary overvoltage threshold, depending on the settings in register 0ch (see tables 2, 3, and 4). [1] 1 = in2 falls below secondary undervoltage threshold or rises above secondary overvoltage threshold, depending on the settings in register 0ch (see tables 2, 3, and 4). [2] 1 = in3 falls below secondary undervoltage threshold or rises above secondary overvoltage threshold, depending on the settings in register 0ch (see tables 2, 3, and 4). [3] 1 = in4 falls below secondary undervoltage threshold or rises above secondary overvoltage threshold, depending on the settings in register 0ch (see tables 2, 3, and 4). [4] 1 = in5 (max6872 only) falls below secondary undervoltage threshold or rises above secondary overvoltage threshold, depending on the settings in register 0ch (see tables 2, 3, and 4). [5] 1 = in6 (max6872 only) falls below secondary undervoltage threshold or rises above secondary overvoltage threshold, depending on the settings in register 0ch (see tables 2, 3, and 4). 61h [7:6] not used. [0] 1 = wd1 asserted. [1] 1 = wd2 asserted. [2] 1 = gpi1 asserted. [3] 1 = gpi2 asserted. [4] 1 = gpi3 asserted. [5] 1 = gpi4 asserted. [6] 1 = mr asserted. 62h [7] not used.
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors 44 ______________________________________________________________________________________ uses for general-purpose inputs (gpi1?pi4) watchdog timer program gpi_ as an input to one of the watchdog timers in the max6872/max6873. the gpi_ input must toggle within the watchdog timeout period, otherwise any programmable output dependent on the watchdog timer asserts. additional manual reset functions the po7 (max6872)/po5 (max6873) programmable outputs allow a single set (product 1 only) of conditions to assert the output. program the set of conditions to depend on one of the gpi_ inputs. any output that depends on gpi_ asserts when gpi_ is held in its active state, effectively acting as a manual reset input. in3 po1 to load +5v gnd max6872 max6873 figure 9. driving high-side n-channel mosfet switches table 28. configuration lock register register address eeprom memory address bit range description [0] 0 = configuration unlocked. 1 = configuration locked. 45h 8045h [7:1] not used. table 29. write disable register register address eeprom memory address bit range description [0] 0 = write not disabled if po1 asserts (max6872). 1 = write disabled if po1 asserts (max6872). set to 0 (max6873). [1] 0 = write not disabled if po2 asserts (max6872). 1 = write disabled if po2 asserts (max6872). set to 0 (max6873). [2] 0 = write not disabled if po3 (max6872)/po1 (max6873) asserts. 1 = write disabled if po3 (max6872)/po1 (max6873) asserts. [3] 0 = write not disabled if po4 (max6872)/po2 (max6873) asserts. 1 = write disabled if po4 (max6872)/po2 (max6873) asserts. [4] 0 = write not disabled if po5 (max6872)/po3 (max6873) asserts. 1 = write disabled if po5 (max6872)/po3 (max6873) asserts. [5] 0 = write not disabled if po6 (max6872)/po4 (max6873) asserts. 1 = write disabled if po6 (max6872)/po4 (max6873) asserts. [6] 0 = write not disabled if po7 (max6872)/po5 (max6873) asserts. 1 = write disabled if po7 (max6872)/po5 (max6873) asserts. 43h 8043h [7] 0 = write not disabled if po8 asserts (max6872). 1 = write disabled if po8 asserts (max6872). set to 0 (max6873).
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 45 32 31 30 29 28 27 26 po1 i.c. in1 in2 in3 in4 in5 25 in6 9 10 11 12 13 14 15 n.c. n.c. margin mr sda scl a0 16 a1 17 18 19 20 21 22 23 gpi4 *exposed paddle internally connected to gnd. *exposed paddle gpi3 gpi2 gpi1 abp dbp n.c. 8 7 6 5 4 3 2 po8 po7 po6 po5 gnd po4 po3 max6872 (7mm x 7mm thin qfn) 1 po2 24 n.c. top view 32 31 30 29 28 27 26 n.c. i.c. in1 in2 in3 in4 n.c. 25 n.c. 9 10 11 12 13 14 15 n.c. n.c. margin mr sda scl a0 16 a1 17 18 19 20 21 22 23 gpi4 *exposed paddle gpi3 gpi2 gpi1 abp dbp n.c. 8 7 6 5 4 3 2 n.c. po5 po4 po3 gnd po2 po1 max6873 (7mm x 7mm thin qfn) 1 n.c. 24 n.c. pin configurations selector guide part voltage-detector inputs general-purpose inputs programmable outputs max6872etj 6 4 8 MAX6873ETJ 4 4 5 other fault signals from ? connect a general-purpose output from a ? to one of the gpi_ inputs to allow interrupts to assert any output of the max6872/max6873. configure one of the pro- grammable outputs to assert on whichever gpi_ input connects to the general-purpose output of the ?. layout and bypassing for better noise immunity, bypass each of the voltage detector inputs to gnd with 0.1? capacitors installed as close to the device as possible. bypass abp and dbp to gnd with 1? capacitors installed as close to the device as possible. abp and dbp are internally generated voltages and should not be used to supply power to external circuitry. configuration latency period a delay of less than 5? occurs between writing to the configuration registers and the time when these changes actually take place, except when changing one of the voltage-detector thresholds. changing a volt- age-detector threshold typically takes 150?. when changing eeprom contents, a software reboot or cycling of power is required for these changes to trans- fer to volatile memory.
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors 46 ______________________________________________________________________________________ max6873 dc-dc 1 dbp po1 in1 dc-dc 2 in3 po2 dc-dc 3 in4 po3 gnd in5 po5 in6 po4 in2 sda sda +5v switched +0.7v +2.5v +3.3v +5v +12v p scl scl po6 reset po7 nmi, ov alert po8 a0 nmi, wd alert gpi1 (wd) logic output r pu r pu dc-dc 4 +12v supply po1 po2 po3 +12v bus input t po1 enable +5v dc-dc converter a1 gpi2 gpi4 gpi3 abp margin mr +12v +5v supply +5v output t po2 enable +2.5v dc-dc converter +2.5v supply +2.5v output t po3 enable +3.3v dc-dc converter +3.3v supply po5 po4 po6 +3.3v output t po5 enable +0.7v dc-dc converter +0.7v supply +0.7v output t po4 enable +5v fet switch +5v supply +5v switched output t po6 system reset typical operating circuit
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors ______________________________________________________________________________________ 47 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 32, 44, 48l qfn .eps proprietary information approval title: document control no. 21-0144 package outline 32, 44, 48, 56l thin qfn, 7x7x0.8mm 1 d rev. 2 e l e l a1 a a2 e/2 e d/2 d detail a d2/2 d2 b l k e2/2 e2 (ne-1) x e (nd-1) x e e c l c l c l c l k dallas semiconductor detail b e l l1 chip information process: bicmos
max6872/max6873 eeprom-programmable, hex/quad, power-supply sequencers/supervisors maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 48 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) proprietary information document control no. approval title: rev. 2 2 21-0144 dallas semiconductor package outline 32, 44, 48, 56l thin qfn, 7x7x0.8mm d

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